diff options
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 2 | ||||
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 2 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 10 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 4 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index b80c1c356..7fcb5431b 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -353,7 +353,7 @@ CacheMemory::profileMiss(const CacheMsg& msg) void CacheMemory::profileGenericRequest(GenericRequestType requestType, - AccessModeType accessType, + RubyAccessMode accessType, PrefetchBit pfBit) { m_profiler_ptr->addGenericStatSample(requestType, diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 1f0ffd500..6e311edc3 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -110,7 +110,7 @@ class CacheMemory : public SimObject void profileMiss(const CacheMsg & msg); void profileGenericRequest(GenericRequestType requestType, - AccessModeType accessType, + RubyAccessMode accessType, PrefetchBit pfBit); void getMemoryValue(const Address& addr, char* value, diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 800352eed..7f916957b 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -644,16 +644,16 @@ Sequencer::issueRequest(const RubyRequest& request) assert(0); } - AccessModeType amtype; + RubyAccessMode amtype; switch(request.access_mode){ case RubyAccessMode_User: - amtype = AccessModeType_UserMode; + amtype = RubyAccessMode_User; break; case RubyAccessMode_Supervisor: - amtype = AccessModeType_SupervisorMode; + amtype = RubyAccessMode_Supervisor; break; case RubyAccessMode_Device: - amtype = AccessModeType_UserMode; + amtype = RubyAccessMode_User; break; default: assert(0); @@ -686,7 +686,7 @@ Sequencer::issueRequest(const RubyRequest& request) #if 0 bool Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type, - AccessModeType access_mode, + RubyAccessMode access_mode, int size, DataBlock*& data_ptr) { CacheMemory *cache = diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 453a8cbae..7793af889 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -32,7 +32,7 @@ #include <iostream> #include "base/hashmap.hh" -#include "mem/protocol/AccessModeType.hh" +#include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/PrefetchBit.hh" @@ -113,7 +113,7 @@ class Sequencer : public RubyPort, public Consumer private: bool tryCacheAccess(const Address& addr, CacheRequestType type, - const Address& pc, AccessModeType access_mode, + const Address& pc, RubyAccessMode access_mode, int size, DataBlock*& data_ptr); void issueRequest(const RubyRequest& request); |