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-rw-r--r--src/mem/ruby/system/CacheRecorder.cc3
-rw-r--r--src/mem/ruby/system/CacheRecorder.hh9
-rw-r--r--src/mem/ruby/system/DMASequencer.cc16
-rw-r--r--src/mem/ruby/system/DMASequencer.hh2
-rw-r--r--src/mem/ruby/system/RubyPort.cc10
-rw-r--r--src/mem/ruby/system/RubyPort.hh4
-rw-r--r--src/mem/ruby/system/Sequencer.cc53
-rw-r--r--src/mem/ruby/system/Sequencer.hh14
-rw-r--r--src/mem/ruby/system/System.cc13
9 files changed, 58 insertions, 66 deletions
diff --git a/src/mem/ruby/system/CacheRecorder.cc b/src/mem/ruby/system/CacheRecorder.cc
index 8e8757967..a2ac6bdf8 100644
--- a/src/mem/ruby/system/CacheRecorder.cc
+++ b/src/mem/ruby/system/CacheRecorder.cc
@@ -145,8 +145,7 @@ CacheRecorder::enqueueNextFetchRequest()
}
void
-CacheRecorder::addRecord(int cntrl, const physical_address_t data_addr,
- const physical_address_t pc_addr,
+CacheRecorder::addRecord(int cntrl, Addr data_addr, Addr pc_addr,
RubyRequestType type, Tick time, DataBlock& data)
{
TraceRecord* rec = (TraceRecord*)malloc(sizeof(TraceRecord) +
diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh
index ad1223dce..a4a7261f4 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -56,8 +56,8 @@ class TraceRecord {
public:
int m_cntrl_id;
Tick m_time;
- physical_address_t m_data_address;
- physical_address_t m_pc_address;
+ Addr m_data_address;
+ Addr m_pc_address;
RubyRequestType m_type;
uint8_t m_data[0];
@@ -74,9 +74,8 @@ class CacheRecorder
uint64_t uncompressed_trace_size,
std::vector<Sequencer*>& SequencerMap,
uint64_t block_size_bytes);
- void addRecord(int cntrl, const physical_address_t data_addr,
- const physical_address_t pc_addr, RubyRequestType type,
- Tick time, DataBlock& data);
+ void addRecord(int cntrl, Addr data_addr, Addr pc_addr,
+ RubyRequestType type, Tick time, DataBlock& data);
uint64 aggregateRecords(uint8_t** data, uint64 size);
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 49e986d76..e263fefdb 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -94,7 +94,7 @@ DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
panic("DMASequencer should never see an inhibited request\n");
assert(isPhysMemAddress(pkt->getAddr()));
- assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
+ assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
RubySystem::getBlockSizeBytes());
// Submit the ruby request
@@ -223,7 +223,7 @@ DMASequencer::makeRequest(PacketPtr pkt)
return RequestStatus_BufferFull;
}
- uint64_t paddr = pkt->getAddr();
+ Addr paddr = pkt->getAddr();
uint8_t* data = pkt->getPtr<uint8_t>();
int len = pkt->getSize();
bool write = pkt->isWrite();
@@ -241,8 +241,8 @@ DMASequencer::makeRequest(PacketPtr pkt)
std::shared_ptr<SequencerMsg> msg =
std::make_shared<SequencerMsg>(clockEdge());
- msg->getPhysicalAddress() = Address(paddr);
- msg->getLineAddress() = line_address(msg->getPhysicalAddress());
+ msg->getPhysicalAddress() = paddr;
+ msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
int offset = paddr & m_data_block_mask;
@@ -280,11 +280,11 @@ DMASequencer::issueNext()
std::shared_ptr<SequencerMsg> msg =
std::make_shared<SequencerMsg>(clockEdge());
- msg->getPhysicalAddress() = Address(active_request.start_paddr +
- active_request.bytes_completed);
+ msg->getPhysicalAddress() = active_request.start_paddr +
+ active_request.bytes_completed;
- assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
- msg->getLineAddress() = line_address(msg->getPhysicalAddress());
+ assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
+ msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
msg->getType() = (active_request.write ? SequencerRequestType_ST :
SequencerRequestType_LD);
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index ee7d578e0..1539c3999 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -76,7 +76,7 @@ class DMASequencer : public MemObject
PortID id, RubySystem *_ruby_system,
bool _access_backing_store);
void hitCallback(PacketPtr pkt);
- void evictionCallback(const Address& address);
+ void evictionCallback(Addr address);
protected:
bool recvTimingReq(PacketPtr pkt);
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 83be9337a..c13aed97e 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -249,7 +249,7 @@ RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
return true;
}
- assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
+ assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
RubySystem::getBlockSizeBytes());
// Submit the ruby request
@@ -299,8 +299,7 @@ RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
}
assert(pkt->getAddr() + pkt->getSize() <=
- line_address(Address(pkt->getAddr())).getAddress() +
- RubySystem::getBlockSizeBytes());
+ makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
if (access_backing_store) {
// The attached physmem contains the official version of data.
@@ -504,14 +503,13 @@ RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
}
void
-RubyPort::ruby_eviction_callback(const Address& address)
+RubyPort::ruby_eviction_callback(Addr address)
{
DPRINTF(RubyPort, "Sending invalidations.\n");
// This request is deleted in the stack-allocated packet destructor
// when this function exits
// TODO: should this really be using funcMasterId?
- RequestPtr req =
- new Request(address.getAddress(), 0, 0, Request::funcMasterId);
+ RequestPtr req = new Request(address, 0, 0, Request::funcMasterId);
// Use a single packet to signal all snooping ports of the invalidation.
// This assumes that snooping ports do NOT modify the packet/request
Packet pkt(req, MemCmd::InvalidateReq);
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 07fca5916..f2841e561 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -81,7 +81,7 @@ class RubyPort : public MemObject
MemSlavePort(const std::string &_name, RubyPort *_port,
bool _access_backing_store, PortID id);
void hitCallback(PacketPtr pkt);
- void evictionCallback(const Address& address);
+ void evictionCallback(Addr address);
protected:
bool recvTimingReq(PacketPtr pkt);
@@ -166,7 +166,7 @@ class RubyPort : public MemObject
protected:
void ruby_hit_callback(PacketPtr pkt);
void testDrainComplete();
- void ruby_eviction_callback(const Address& address);
+ void ruby_eviction_callback(Addr address);
/**
* Called by the PIO port when receiving a timing response.
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 36bd9cd62..305758798 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -96,9 +96,9 @@ Sequencer::wakeup()
continue;
panic("Possible Deadlock detected. Aborting!\n"
- "version: %d request.paddr: 0x%x m_readRequestTable: %d "
- "current time: %u issue_time: %d difference: %d\n", m_version,
- Address(request->pkt->getAddr()), m_readRequestTable.size(),
+ "version: %d request.paddr: 0x%x m_readRequestTable: %d "
+ "current time: %u issue_time: %d difference: %d\n", m_version,
+ request->pkt->getAddr(), m_readRequestTable.size(),
current_time * clockPeriod(), request->issue_time * clockPeriod(),
(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
}
@@ -111,9 +111,9 @@ Sequencer::wakeup()
continue;
panic("Possible Deadlock detected. Aborting!\n"
- "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
- "current time: %u issue_time: %d difference: %d\n", m_version,
- Address(request->pkt->getAddr()), m_writeRequestTable.size(),
+ "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
+ "current time: %u issue_time: %d difference: %d\n", m_version,
+ request->pkt->getAddr(), m_writeRequestTable.size(),
current_time * clockPeriod(), request->issue_time * clockPeriod(),
(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
}
@@ -222,8 +222,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
}
- Address line_addr(pkt->getAddr());
- line_addr.makeLineAddress();
+ Addr line_addr = makeLineAddress(pkt->getAddr());
// Create a default entry, mapping the address to NULL, the cast is
// there to make gcc 4.4 happy
RequestTable::value_type default_entry(line_addr,
@@ -299,8 +298,7 @@ Sequencer::removeRequest(SequencerRequest* srequest)
assert(m_outstanding_count ==
m_writeRequestTable.size() + m_readRequestTable.size());
- Address line_addr(srequest->pkt->getAddr());
- line_addr.makeLineAddress();
+ Addr line_addr = makeLineAddress(srequest->pkt->getAddr());
if ((srequest->m_type == RubyRequestType_ST) ||
(srequest->m_type == RubyRequestType_RMW_Read) ||
(srequest->m_type == RubyRequestType_RMW_Write) ||
@@ -317,7 +315,7 @@ Sequencer::removeRequest(SequencerRequest* srequest)
}
void
-Sequencer::invalidateSC(const Address& address)
+Sequencer::invalidateSC(Addr address)
{
RequestTable::iterator i = m_writeRequestTable.find(address);
if (i != m_writeRequestTable.end()) {
@@ -331,7 +329,7 @@ Sequencer::invalidateSC(const Address& address)
}
bool
-Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
+Sequencer::handleLlsc(Addr address, SequencerRequest* request)
{
//
// The success flag indicates whether the LLSC operation was successful.
@@ -422,14 +420,14 @@ Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
}
void
-Sequencer::writeCallback(const Address& address, DataBlock& data,
+Sequencer::writeCallback(Addr address, DataBlock& data,
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
const Cycles firstResponseTime)
{
- assert(address == line_address(address));
- assert(m_writeRequestTable.count(line_address(address)));
+ assert(address == makeLineAddress(address));
+ assert(m_writeRequestTable.count(makeLineAddress(address)));
RequestTable::iterator i = m_writeRequestTable.find(address);
assert(i != m_writeRequestTable.end());
@@ -469,14 +467,14 @@ Sequencer::writeCallback(const Address& address, DataBlock& data,
}
void
-Sequencer::readCallback(const Address& address, DataBlock& data,
+Sequencer::readCallback(Addr address, DataBlock& data,
bool externalHit, const MachineType mach,
Cycles initialRequestTime,
Cycles forwardRequestTime,
Cycles firstResponseTime)
{
- assert(address == line_address(address));
- assert(m_readRequestTable.count(line_address(address)));
+ assert(address == makeLineAddress(address));
+ assert(m_readRequestTable.count(makeLineAddress(address)));
RequestTable::iterator i = m_readRequestTable.find(address);
assert(i != m_readRequestTable.end());
@@ -501,9 +499,8 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
const Cycles firstResponseTime)
{
PacketPtr pkt = srequest->pkt;
- Address request_address(pkt->getAddr());
- Address request_line_address(pkt->getAddr());
- request_line_address.makeLineAddress();
+ Addr request_address(pkt->getAddr());
+ Addr request_line_address = makeLineAddress(pkt->getAddr());
RubyRequestType type = srequest->m_type;
Cycles issued_time = srequest->issue_time;
@@ -522,7 +519,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
initialRequestTime, forwardRequestTime,
firstResponseTime, curCycle());
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
curTick(), m_version, "Seq",
llscSuccess ? "Done" : "SC_Failed", "", "",
request_address, total_latency);
@@ -530,7 +527,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
// update the data unless it is a non-data-carrying flush
if (RubySystem::getWarmupEnabled()) {
data.setData(pkt->getConstPtr<uint8_t>(),
- request_address.getOffset(), pkt->getSize());
+ getOffset(request_address), pkt->getSize());
} else if (!pkt->isFlush()) {
if ((type == RubyRequestType_LD) ||
(type == RubyRequestType_IFETCH) ||
@@ -538,12 +535,12 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
(type == RubyRequestType_Locked_RMW_Read) ||
(type == RubyRequestType_Load_Linked)) {
memcpy(pkt->getPtr<uint8_t>(),
- data.getData(request_address.getOffset(), pkt->getSize()),
+ data.getData(getOffset(request_address), pkt->getSize()),
pkt->getSize());
DPRINTF(RubySequencer, "read data %s\n", data);
} else {
data.setData(pkt->getConstPtr<uint8_t>(),
- request_address.getOffset(), pkt->getSize());
+ getOffset(request_address), pkt->getSize());
DPRINTF(RubySequencer, "set data %s\n", data);
}
}
@@ -690,7 +687,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
RubyAccessMode_Supervisor, pkt,
PrefetchBit_No, proc_id);
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
curTick(), m_version, "Seq", "Begin", "", "",
msg->getPhysicalAddress(),
RubyRequestType_to_string(secondary_type));
@@ -743,7 +740,7 @@ Sequencer::print(ostream& out) const
// upgraded when invoked, coherence violations will be checked for the
// given block
void
-Sequencer::checkCoherence(const Address& addr)
+Sequencer::checkCoherence(Addr addr)
{
#ifdef CHECK_COHERENCE
m_ruby_system->checkGlobalCoherenceInvariant(addr);
@@ -758,7 +755,7 @@ Sequencer::recordRequestType(SequencerRequestType requestType) {
void
-Sequencer::evictionCallback(const Address& address)
+Sequencer::evictionCallback(Addr address)
{
ruby_eviction_callback(address);
}
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 505b3f3bc..c4ed6f21e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -68,7 +68,7 @@ class Sequencer : public RubyPort
void collateStats();
void regStats();
- void writeCallback(const Address& address,
+ void writeCallback(Addr address,
DataBlock& data,
const bool externalHit = false,
const MachineType mach = MachineType_NUM,
@@ -76,7 +76,7 @@ class Sequencer : public RubyPort
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
- void readCallback(const Address& address,
+ void readCallback(Addr address,
DataBlock& data,
const bool externalHit = false,
const MachineType mach = MachineType_NUM,
@@ -95,12 +95,12 @@ class Sequencer : public RubyPort
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
- void checkCoherence(const Address& address);
+ void checkCoherence(Addr address);
void markRemoved();
void removeRequest(SequencerRequest* request);
- void evictionCallback(const Address& address);
- void invalidateSC(const Address& address);
+ void evictionCallback(Addr address);
+ void invalidateSC(Addr address);
void recordRequestType(SequencerRequestType requestType);
Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
@@ -167,7 +167,7 @@ class Sequencer : public RubyPort
Cycles completionTime);
RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
- bool handleLlsc(const Address& address, SequencerRequest* request);
+ bool handleLlsc(Addr address, SequencerRequest* request);
// Private copy constructor and assignment operator
Sequencer(const Sequencer& obj);
@@ -187,7 +187,7 @@ class Sequencer : public RubyPort
Cycles m_data_cache_hit_latency;
Cycles m_inst_cache_hit_latency;
- typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
+ typedef m5::hash_map<Addr, SequencerRequest*> RequestTable;
RequestTable m_writeRequestTable;
RequestTable m_readRequestTable;
// Global outstanding request count, across all request tables
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index 98cf50e9c..c00082010 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -393,14 +393,13 @@ RubySystem::resetStats()
bool
RubySystem::functionalRead(PacketPtr pkt)
{
- Address address(pkt->getAddr());
- Address line_address(address);
- line_address.makeLineAddress();
+ Addr address(pkt->getAddr());
+ Addr line_address = makeLineAddress(address);
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
- DPRINTF(RubySystem, "Functional Read request for %s\n",address);
+ DPRINTF(RubySystem, "Functional Read request for %s\n", address);
unsigned int num_ro = 0;
unsigned int num_rw = 0;
@@ -477,12 +476,12 @@ RubySystem::functionalRead(PacketPtr pkt)
bool
RubySystem::functionalWrite(PacketPtr pkt)
{
- Address addr(pkt->getAddr());
- Address line_addr = line_address(addr);
+ Addr addr(pkt->getAddr());
+ Addr line_addr = makeLineAddress(addr);
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
- DPRINTF(RubySystem, "Functional Write request for %s\n",addr);
+ DPRINTF(RubySystem, "Functional Write request for %s\n", addr);
uint32_t M5_VAR_USED num_functional_writes = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-03 16:55:13 +0000