diff options
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 15 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 1 |
2 files changed, 15 insertions, 1 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index f00f8407a..54fb83dd0 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -306,6 +306,20 @@ Sequencer::removeRequest(SequencerRequest* srequest) markRemoved(); } +void +Sequencer::invalidateSC(const Address& address) +{ + RequestTable::iterator i = m_writeRequestTable.find(address); + if (i != m_writeRequestTable.end()) { + SequencerRequest* request = i->second; + // The controller has lost the coherence permissions, hence the lock + // on the cache line maintained by the cache should be cleared. + if (request->m_type == RubyRequestType_Store_Conditional) { + m_dataCache_ptr->clearLocked(address); + } + } +} + bool Sequencer::handleLlsc(const Address& address, SequencerRequest* request) { @@ -392,7 +406,6 @@ Sequencer::writeCallback(const Address& address, (request->m_type == RubyRequestType_Locked_RMW_Write) || (request->m_type == RubyRequestType_FLUSH)); - // // For Alpha, properly handle LL, SC, and write requests with respect to // locked cache blocks. diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index b3ec4d10a..782b776f9 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -116,6 +116,7 @@ class Sequencer : public RubyPort void markRemoved(); void removeRequest(SequencerRequest* request); void evictionCallback(const Address& address); + void invalidateSC(const Address& address); void recordRequestType(SequencerRequestType requestType); |