3 files changed, 10 insertions, 1 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 6b0f6e49f..a5f1a06fa 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -77,6 +77,8 @@ Sequencer::Sequencer(const Params *p)
     assert(m_deadlock_threshold > 0);
     assert(m_instCache_ptr != NULL);
     assert(m_dataCache_ptr != NULL);
+
+    m_usingNetworkTester = p->using_network_tester;
 }
 
 Sequencer::~Sequencer()
@@ -390,7 +392,11 @@ Sequencer::writeCallback(const Address& address,
     // For Alpha, properly handle LL, SC, and write requests with respect to
     // locked cache blocks.
     //
-    bool success = handleLlsc(address, request);
+    // Not valid for Network_test protocl
+    //
+    bool success = true;
+    if(!m_usingNetworkTester)
+        success = handleLlsc(address, request);
 
     if (request->ruby_request.type == RubyRequestType_Locked_RMW_Read) {
         m_controller->blockOnQueue(address, m_mandatory_q_ptr);
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 14b6997e8..ff3a0d5b1 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -152,6 +152,8 @@ class Sequencer : public RubyPort, public Consumer
     int m_load_waiting_on_store_cycles;
     int m_load_waiting_on_load_cycles;
 
+    bool m_usingNetworkTester;
+
     class SequencerWakeupEvent : public Event
     {
       private:
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index f6d847e10..16fb795f8 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -40,6 +40,7 @@ class RubyPort(MemObject):
     physmem = Param.PhysicalMemory("")
     physMemPort = Port("port to physical memory")
     using_ruby_tester = Param.Bool(False, "")
+    using_network_tester = Param.Bool(False, "")
     access_phys_mem = Param.Bool(True,
         "should the rubyport atomically update phys_mem")