diff options
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 15 | ||||
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 5 |
2 files changed, 18 insertions, 2 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index c9de85961..9102d1963 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -375,8 +375,19 @@ CacheMemory::setMRU(const Address& address) void CacheMemory::profileMiss(const CacheMsg& msg) { - m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(), - msg.getSize(), msg.getPrefetch()); + m_profiler_ptr->addCacheStatSample(msg.getType(), + msg.getAccessMode(), + msg.getPrefetch()); +} + +void +CacheMemory::profileGenericRequest(GenericRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit) +{ + m_profiler_ptr->addGenericStatSample(requestType, + accessType, + pfBit); } void diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index f004b8310..c1d49f784 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -37,6 +37,7 @@ #include "mem/protocol/AccessPermission.hh" #include "mem/protocol/CacheMsg.hh" #include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/MachineType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/DataBlock.hh" @@ -112,6 +113,10 @@ class CacheMemory : public SimObject void profileMiss(const CacheMsg & msg); + void profileGenericRequest(GenericRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit); + void getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); void setMemoryValue(const Address& addr, char* value, |