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-rw-r--r--src/mem/ruby/common/TypeDefines.hh1
-rw-r--r--src/mem/ruby/profiler/Profiler.cc30
-rw-r--r--src/mem/ruby/profiler/Profiler.hh32
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc2
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh2
-rw-r--r--src/mem/ruby/slicc_interface/RubySlicc_Util.hh34
-rw-r--r--src/mem/ruby/structures/Prefetcher.cc2
-rw-r--r--src/mem/ruby/system/Sequencer.cc34
-rw-r--r--src/mem/ruby/system/Sequencer.hh44
-rw-r--r--src/mem/ruby/system/TBETable.hh3
-rw-r--r--src/mem/ruby/system/TimerTable.cc2
-rw-r--r--src/mem/ruby/system/TimerTable.hh2
12 files changed, 71 insertions, 117 deletions
diff --git a/src/mem/ruby/common/TypeDefines.hh b/src/mem/ruby/common/TypeDefines.hh
index b031a62d3..af1a6ca4c 100644
--- a/src/mem/ruby/common/TypeDefines.hh
+++ b/src/mem/ruby/common/TypeDefines.hh
@@ -31,7 +31,6 @@
#define TYPEDEFINES_H
typedef unsigned long long uint64;
-
typedef long long int64;
typedef int64 Time;
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 165561fe8..e15285784 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -270,7 +270,7 @@ Profiler::printStats(ostream& out, bool short_stats)
double minutes = seconds / 60.0;
double hours = minutes / 60.0;
double days = hours / 24.0;
- Time ruby_cycles = g_system_ptr->getTime()-m_ruby_start;
+ Cycles ruby_cycles = g_system_ptr->getTime()-m_ruby_start;
if (!short_stats) {
out << "Elapsed_time_in_seconds: " << seconds << endl;
@@ -609,7 +609,7 @@ Profiler::profileSharing(const Address& addr, AccessType type,
}
void
-Profiler::profilePFWait(Time waitTime)
+Profiler::profilePFWait(Cycles waitTime)
{
m_prefetchWaitHistogram.add(waitTime);
}
@@ -622,7 +622,7 @@ Profiler::bankBusy()
// non-zero cycle demand request
void
-Profiler::missLatency(Time cycles,
+Profiler::missLatency(Cycles cycles,
RubyRequestType type,
const GenericMachineType respondingMach)
{
@@ -633,11 +633,11 @@ Profiler::missLatency(Time cycles,
}
void
-Profiler::missLatencyWcc(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime)
+Profiler::missLatencyWcc(Cycles issuedTime,
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime,
+ Cycles completionTime)
{
if ((issuedTime <= initialRequestTime) &&
(initialRequestTime <= forwardRequestTime) &&
@@ -659,11 +659,11 @@ Profiler::missLatencyWcc(Time issuedTime,
}
void
-Profiler::missLatencyDir(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime)
+Profiler::missLatencyDir(Cycles issuedTime,
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime,
+ Cycles completionTime)
{
if ((issuedTime <= initialRequestTime) &&
(initialRequestTime <= forwardRequestTime) &&
@@ -686,13 +686,13 @@ Profiler::missLatencyDir(Time issuedTime,
// non-zero cycle prefetch request
void
-Profiler::swPrefetchLatency(Time cycles,
- RubyRequestType type,
+Profiler::swPrefetchLatency(Cycles cycles, RubyRequestType type,
const GenericMachineType respondingMach)
{
m_allSWPrefetchLatencyHistogram.add(cycles);
m_SWPrefetchLatencyHistograms[type].add(cycles);
m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles);
+
if (respondingMach == GenericMachineType_Directory ||
respondingMach == GenericMachineType_NUM) {
m_SWPrefetchL2MissLatencyHistogram.add(cycles);
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index ecd57c035..421e8fe55 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -125,29 +125,23 @@ class Profiler : public SimObject
void startTransaction(int cpu);
void endTransaction(int cpu);
- void profilePFWait(Time waitTime);
+ void profilePFWait(Cycles waitTime);
void controllerBusy(MachineID machID);
void bankBusy();
- void missLatency(Time t,
- RubyRequestType type,
+ void missLatency(Cycles t, RubyRequestType type,
const GenericMachineType respondingMach);
- void missLatencyWcc(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime);
+ void missLatencyWcc(Cycles issuedTime, Cycles initialRequestTime,
+ Cycles forwardRequestTime, Cycles firstResponseTime,
+ Cycles completionTime);
- void missLatencyDir(Time issuedTime,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime,
- Time completionTime);
+ void missLatencyDir(Cycles issuedTime, Cycles initialRequestTime,
+ Cycles forwardRequestTime, Cycles firstResponseTime,
+ Cycles completionTime);
- void swPrefetchLatency(Time t,
- RubyRequestType type,
+ void swPrefetchLatency(Cycles t, RubyRequestType type,
const GenericMachineType respondingMach);
void sequencerRequests(int num) { m_sequencer_requests.add(num); }
@@ -158,11 +152,7 @@ class Profiler : public SimObject
bool watchAddress(Address addr);
// return Ruby's start time
- Time
- getRubyStartTime()
- {
- return m_ruby_start;
- }
+ Cycles getRubyStartTime() { return m_ruby_start; }
// added by SS
bool getHotLines() { return m_hot_lines; }
@@ -186,7 +176,7 @@ class Profiler : public SimObject
std::ostream* m_periodic_output_file_ptr;
int64_t m_stats_period;
- Time m_ruby_start;
+ Cycles m_ruby_start;
time_t m_real_time_start_time;
int64_t m_busyBankCount;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index bcd09796a..9a0ee2b2b 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -73,7 +73,7 @@ AbstractController::profileRequest(const std::string &request)
}
void
-AbstractController::profileMsgDelay(uint32_t virtualNetwork, Time delay)
+AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
{
assert(virtualNetwork < m_delayVCHistogram.size());
m_delayHistogram.add(delay);
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 44981a7e8..ba0c4b683 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -101,7 +101,7 @@ class AbstractController : public ClockedObject, public Consumer
//! Profiles original cache requests including PUTs
void profileRequest(const std::string &request);
//! Profiles the delay associated with messages.
- void profileMsgDelay(uint32_t virtualNetwork, Time delay);
+ void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
protected:
int m_transitions_per_cycle;
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 622efd04c..75048136f 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -46,12 +46,7 @@ random(int n)
return random() % n;
}
-inline Time
-zero_time()
-{
- return 0;
-}
-
+inline Cycles zero_time() { return Cycles(0); }
inline Cycles TimeToCycles(Time t) { return Cycles(t); }
inline NodeID
@@ -68,33 +63,6 @@ IDToInt(NodeID id)
return nodenum;
}
-inline Time
-getTimeModInt(Time time, int modulus)
-{
- return time % modulus;
-}
-
-inline Time
-getTimePlusInt(Time addend1, int addend2)
-{
- return (Time) addend1 + addend2;
-}
-
-inline Time
-getTimeMinusTime(Time t1, Time t2)
-{
- assert(t1 >= t2);
- return t1 - t2;
-}
-
-// Return type for time_to_int is "Time" and not "int" so we get a
-// 64-bit integer
-inline Time
-time_to_int(Time time)
-{
- return time;
-}
-
// Appends an offset to an address
inline Address
setOffset(Address addr, int offset)
diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc
index 47caf1cc8..05a1d8e62 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/Prefetcher.cc
@@ -257,7 +257,7 @@ uint32_t
Prefetcher::getLRUindex(void)
{
uint32_t lru_index = 0;
- Time lru_access = m_array[lru_index].m_use_time;
+ Cycles lru_access = m_array[lru_index].m_use_time;
for (uint32_t i = 0; i < m_num_streams; i++) {
if (!m_array[i].m_is_valid) {
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 3481369bb..94ad42d9d 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -359,19 +359,19 @@ Sequencer::writeCallback(const Address& address, DataBlock& data)
void
Sequencer::writeCallback(const Address& address,
- GenericMachineType mach,
+ GenericMachineType mach,
DataBlock& data)
{
- writeCallback(address, mach, data, 0, 0, 0);
+ writeCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
}
void
Sequencer::writeCallback(const Address& address,
- GenericMachineType mach,
+ GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime)
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime)
{
assert(address == line_address(address));
assert(m_writeRequestTable.count(line_address(address)));
@@ -410,7 +410,7 @@ Sequencer::writeCallback(const Address& address,
m_controller->unblock(address);
}
- hitCallback(request, mach, data, success,
+ hitCallback(request, mach, data, success,
initialRequestTime, forwardRequestTime, firstResponseTime);
}
@@ -425,16 +425,16 @@ Sequencer::readCallback(const Address& address,
GenericMachineType mach,
DataBlock& data)
{
- readCallback(address, mach, data, 0, 0, 0);
+ readCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
}
void
Sequencer::readCallback(const Address& address,
GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime)
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime)
{
assert(address == line_address(address));
assert(m_readRequestTable.count(line_address(address)));
@@ -449,7 +449,7 @@ Sequencer::readCallback(const Address& address,
assert((request->m_type == RubyRequestType_LD) ||
(request->m_type == RubyRequestType_IFETCH));
- hitCallback(request, mach, data, true,
+ hitCallback(request, mach, data, true,
initialRequestTime, forwardRequestTime, firstResponseTime);
}
@@ -458,16 +458,16 @@ Sequencer::hitCallback(SequencerRequest* srequest,
GenericMachineType mach,
DataBlock& data,
bool success,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime)
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime)
{
PacketPtr pkt = srequest->pkt;
Address request_address(pkt->getAddr());
Address request_line_address(pkt->getAddr());
request_line_address.makeLineAddress();
RubyRequestType type = srequest->m_type;
- Time issued_time = srequest->issue_time;
+ Cycles issued_time = srequest->issue_time;
// Set this cache entry to the most recently used
if (type == RubyRequestType_IFETCH) {
@@ -477,7 +477,7 @@ Sequencer::hitCallback(SequencerRequest* srequest,
}
assert(curCycle() >= issued_time);
- Time miss_latency = curCycle() - issued_time;
+ Cycles miss_latency = curCycle() - issued_time;
// Profile the miss latency for all non-zero demand misses
if (miss_latency != 0) {
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 3fccd2566..b3ec4d10a 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -70,29 +70,29 @@ class Sequencer : public RubyPort
void writeCallback(const Address& address, DataBlock& data);
- void writeCallback(const Address& address,
- GenericMachineType mach,
+ void writeCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data);
- void writeCallback(const Address& address,
- GenericMachineType mach,
+ void writeCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime);
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime);
void readCallback(const Address& address, DataBlock& data);
- void readCallback(const Address& address,
- GenericMachineType mach,
+ void readCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data);
- void readCallback(const Address& address,
- GenericMachineType mach,
+ void readCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime);
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime);
RequestStatus makeRequest(PacketPtr pkt);
bool empty() const;
@@ -122,13 +122,13 @@ class Sequencer : public RubyPort
private:
void issueRequest(PacketPtr pkt, RubyRequestType type);
- void hitCallback(SequencerRequest* request,
+ void hitCallback(SequencerRequest* request,
GenericMachineType mach,
DataBlock& data,
bool success,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime);
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime);
RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
@@ -152,10 +152,10 @@ class Sequencer : public RubyPort
int m_outstanding_count;
bool m_deadlock_check_scheduled;
- int m_store_waiting_on_load_cycles;
- int m_store_waiting_on_store_cycles;
- int m_load_waiting_on_store_cycles;
- int m_load_waiting_on_load_cycles;
+ uint32_t m_store_waiting_on_load_cycles;
+ uint32_t m_store_waiting_on_store_cycles;
+ uint32_t m_load_waiting_on_store_cycles;
+ uint32_t m_load_waiting_on_load_cycles;
bool m_usingNetworkTester;
diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh
index fa4493757..018da6cbb 100644
--- a/src/mem/ruby/system/TBETable.hh
+++ b/src/mem/ruby/system/TBETable.hh
@@ -33,9 +33,6 @@
#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/profiler/Profiler.hh"
-#include "mem/ruby/system/System.hh"
template<class ENTRY>
class TBETable
diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc
index d87f11662..d29491611 100644
--- a/src/mem/ruby/system/TimerTable.cc
+++ b/src/mem/ruby/system/TimerTable.cc
@@ -31,13 +31,13 @@
#include "mem/ruby/system/TimerTable.hh"
TimerTable::TimerTable()
+ : m_next_time(0)
{
m_consumer_ptr = NULL;
m_clockobj_ptr = NULL;
m_next_valid = false;
m_next_address = Address(0);
- m_next_time = 0;
}
bool
diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh
index 95af2eaa7..b271d3e37 100644
--- a/src/mem/ruby/system/TimerTable.hh
+++ b/src/mem/ruby/system/TimerTable.hh
@@ -85,7 +85,7 @@ class TimerTable
typedef std::map<Address, Cycles> AddressMap;
AddressMap m_map;
mutable bool m_next_valid;
- mutable Time m_next_time; // Only valid if m_next_valid is true
+ mutable Cycles m_next_time; // Only valid if m_next_valid is true
mutable Address m_next_address; // Only valid if m_next_valid is true
//! Object used for querying time.
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 03:42:19 +0000