2 files changed, 20 insertions, 26 deletions

diff --git a/src/mem/ruby/system/BankedArray.cc b/src/mem/ruby/system/BankedArray.cc
index 8af0701a5..df7852a0e 100644
--- a/src/mem/ruby/system/BankedArray.cc
+++ b/src/mem/ruby/system/BankedArray.cc
@@ -29,15 +29,12 @@
  *
  */
 
-#include <vector>
-
 #include "base/intmath.hh"
-#include "mem/ruby/common/TypeDefines.hh"
 #include "mem/ruby/system/BankedArray.hh"
-#include "sim/eventq.hh"
+#include "mem/ruby/system/System.hh"
 
-BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit) :
-    EventManager(&mainEventQueue)
+BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
+                         unsigned int startIndexBit)
 {
     this->banks = banks;
     this->accessLatency = accessLatency;
@@ -59,19 +56,21 @@ BankedArray::tryAccess(Index idx)
     unsigned int bank = mapIndexToBank(idx);
     assert(bank < banks);
 
-    if (busyBanks[bank].scheduled()) {
-        if (!(busyBanks[bank].startAccess == curTick() && busyBanks[bank].idx == idx)) {
+    if (busyBanks[bank].endAccess >= curTick()) {
+        if (!(busyBanks[bank].startAccess == curTick() &&
+            busyBanks[bank].idx == idx)) {
             return false;
         } else {
-            return true;  // We tried to allocate resources twice in the same cycle for the same addr
+            // We tried to allocate resources twice
+            // in the same cycle for the same addr
+            return true;
         }
     }
 
     busyBanks[bank].idx = idx;
     busyBanks[bank].startAccess = curTick();
-
-    // substract 1 so that next cycle the resource available
-    schedule(busyBanks[bank], curTick()+accessLatency-1);
+    busyBanks[bank].endAccess = curTick() +
+        (accessLatency-1) * g_system_ptr->clockPeriod();
 
     return true;
 }
diff --git a/src/mem/ruby/system/BankedArray.hh b/src/mem/ruby/system/BankedArray.hh
index 7ebf39dfb..89007befa 100644
--- a/src/mem/ruby/system/BankedArray.hh
+++ b/src/mem/ruby/system/BankedArray.hh
@@ -35,37 +35,32 @@
 #include <vector>
 
 #include "mem/ruby/common/TypeDefines.hh"
-#include "sim/eventq.hh"
+#include "sim/core.hh"
 
-
-
-class BankedArray : public EventManager
+class BankedArray
 {
-private:
+  private:
     unsigned int banks;
     Cycles accessLatency;
     unsigned int bankBits;
     unsigned int startIndexBit;
 
-    //std::vector<bool> busyBanks;
-
-    class TickEvent : public Event
+    class AccessRecord
     {
-    public:
-        TickEvent() : Event() {}
-        void process() {}
+      public:
+        AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
         Index idx;
         Tick startAccess;
+        Tick endAccess;
     };
-    friend class TickEvent;
 
     // If the tick event is scheduled then the bank is busy
     // otherwise, schedule the event and wait for it to complete
-    std::vector<TickEvent> busyBanks;
+    std::vector<AccessRecord> busyBanks;
 
     unsigned int mapIndexToBank(Index idx);
 
-public:
+  public:
     BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
 
     // Note: We try the access based on the cache index, not the address