diff options
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 29 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 25 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 1 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/system/Sequencer.py | 2 |
5 files changed, 55 insertions, 4 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 305228a8f..4ecdb02f3 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -49,6 +49,8 @@ RubyPort::RubyPort(const Params *p) m_request_cnt = 0; pio_port = NULL; physMemPort = NULL; + + m_usingRubyTester = p->using_ruby_tester; } void @@ -108,6 +110,7 @@ RubyPort::M5Port::M5Port(const std::string &_name, { DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name); ruby_port = _port; + _onRetryList = false; } Tick @@ -256,9 +259,18 @@ RubyPort::M5Port::recvTiming(PacketPtr pkt) // Otherwise, we need to delete the senderStatus we just created and return // false. if (requestStatus == RequestStatus_Issued) { + DPRINTF(MemoryAccess, "Request %x issued\n", pkt->getAddr()); return true; } + // + // Unless one is using the ruby tester, record the stalled M5 port for + // later retry when the sequencer becomes free. + // + if (!ruby_port->m_usingRubyTester) { + ruby_port->addToRetryList(this); + } + DPRINTF(MemoryAccess, "Request for address %#x did not issue because %s\n", pkt->getAddr(), RequestStatus_to_string(requestStatus)); @@ -283,6 +295,23 @@ RubyPort::ruby_hit_callback(PacketPtr pkt) delete senderState; port->hitCallback(pkt); + + // + // If we had to stall the M5Ports, wake them up because the sequencer + // likely has free resources now. + // + if (waitingOnSequencer) { + for (std::list<M5Port*>::iterator i = retryList.begin(); + i != retryList.end(); ++i) { + (*i)->sendRetry(); + (*i)->onRetryList(false); + DPRINTF(MemoryAccess, + "Sequencer may now be free. SendRetry to port %s\n", + (*i)->name()); + } + retryList.clear(); + waitingOnSequencer = false; + } } void diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index a2316781a..a96e9f6ac 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -50,12 +50,19 @@ class RubyPort : public MemObject { private: RubyPort *ruby_port; + bool _onRetryList; public: M5Port(const std::string &_name, RubyPort *_port); bool sendTiming(PacketPtr pkt); void hitCallback(PacketPtr pkt); unsigned deviceBlockSize() const; + + bool onRetryList() + { return _onRetryList; } + + void onRetryList(bool newVal) + { _onRetryList = newVal; } protected: virtual bool recvTiming(PacketPtr pkt); @@ -118,14 +125,32 @@ class RubyPort : public MemObject AbstractController* m_controller; MessageBuffer* m_mandatory_q_ptr; PioPort* pio_port; + bool m_usingRubyTester; private: + void addToRetryList(M5Port * port) + { + if (!port->onRetryList()) { + port->onRetryList(true); + retryList.push_back(port); + waitingOnSequencer = true; + } + } + uint16_t m_port_id; uint64_t m_request_cnt; M5Port* physMemPort; PhysicalMemory* physmem; + + // + // Based on similar code in the M5 bus. Stores pointers to those ports + // that should be called when the Sequencer becomes available after a stall. + // + std::list<M5Port*> retryList; + + bool waitingOnSequencer; }; #endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 97122dc69..0c9d4194e 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -72,7 +72,6 @@ Sequencer::Sequencer(const Params *p) m_dataCache_ptr = p->dcache; m_max_outstanding_requests = p->max_outstanding_requests; m_deadlock_threshold = p->deadlock_threshold; - m_usingRubyTester = p->using_ruby_tester; assert(m_max_outstanding_requests > 0); assert(m_deadlock_threshold > 0); diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 4ab85dac8..453a8cbae 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -152,8 +152,6 @@ class Sequencer : public RubyPort, public Consumer int m_load_waiting_on_store_cycles; int m_load_waiting_on_load_cycles; - bool m_usingRubyTester; - class SequencerWakeupEvent : public Event { private: diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 8b6128f56..d7f9aa1a7 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -39,6 +39,7 @@ class RubyPort(MemObject): pio_port = Port("Ruby_pio_port") physmem = Param.PhysicalMemory("") physMemPort = Port("port to physical memory") + using_ruby_tester = Param.Bool(False, "") class RubySequencer(RubyPort): type = 'RubySequencer' @@ -49,7 +50,6 @@ class RubySequencer(RubyPort): "max requests (incl. prefetches) outstanding") deadlock_threshold = Param.Int(500000, "max outstanding cycles for a request before deadlock/livelock declared") - using_ruby_tester = Param.Bool(False, "") class DMASequencer(RubyPort): type = 'DMASequencer' |