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-rw-r--r--src/mem/ruby/config/MOESI_CMP_directory.rb3
-rw-r--r--src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh6
2 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/ruby/config/MOESI_CMP_directory.rb b/src/mem/ruby/config/MOESI_CMP_directory.rb
index 936eb8e80..34f7c1776 100644
--- a/src/mem/ruby/config/MOESI_CMP_directory.rb
+++ b/src/mem/ruby/config/MOESI_CMP_directory.rb
@@ -26,14 +26,13 @@ class MOESI_CMP_directory_L1CacheController < L1CacheController
num_block_bits = log_int(RubySystem.block_size_bytes)
l2_select_low_bit = num_block_bits
- l2_select_high_bit = num_block_bits + num_select_bits - 1
vec = super()
vec += " icache " + @icache.obj_name
vec += " dcache " + @dcache.obj_name
vec += " request_latency "+request_latency().to_s
vec += " l2_select_low_bit " + l2_select_low_bit.to_s
- vec += " l2_select_high_bit " + l2_select_high_bit.to_s
+ vec += " l2_select_num_bits " + num_select_bits.to_s
return vec
end
end
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index a6d99ada9..96405c8dd 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -86,10 +86,12 @@ MachineID map_Address_to_DMA(const Address & addr)
}
inline
-MachineID mapAddressToRange(const Address & addr, MachineType type, int low_bit, int high_bit)
+MachineID mapAddressToRange(const Address & addr, MachineType type, int low_bit, int num_bits)
{
MachineID mach = {type, 0};
- mach.num = addr.bitSelect(low_bit, high_bit);
+ if (num_bits == 0)
+ return mach;
+ mach.num = addr.bitSelect(low_bit, low_bit+num_bits-1);
return mach;
}