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-rw-r--r--src/mem/ruby/common/Address.cc10
-rw-r--r--src/mem/ruby/common/Address.hh1
-rw-r--r--src/mem/ruby/network/MessageBuffer.cc4
-rw-r--r--src/mem/ruby/slicc_interface/AbstractCacheEntry.cc6
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc2
-rw-r--r--src/mem/ruby/slicc_interface/RubyRequest.cc6
-rw-r--r--src/mem/ruby/structures/CacheMemory.cc22
-rw-r--r--src/mem/ruby/structures/DirectoryMemory.cc4
-rw-r--r--src/mem/ruby/structures/Prefetcher.cc10
-rw-r--r--src/mem/ruby/system/RubySystem.cc4
-rw-r--r--src/mem/ruby/system/Sequencer.cc4
11 files changed, 42 insertions, 31 deletions
diff --git a/src/mem/ruby/common/Address.cc b/src/mem/ruby/common/Address.cc
index d9fadf128..f0aa71ac6 100644
--- a/src/mem/ruby/common/Address.cc
+++ b/src/mem/ruby/common/Address.cc
@@ -121,3 +121,13 @@ makeNextStrideAddress(Addr addr, int stride)
return maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
+ RubySystem::getBlockSizeBytes() * stride;
}
+
+std::string
+printAddress(Addr addr)
+{
+ std::stringstream out;
+ out << "[" << std::hex << "0x" << addr << "," << " line 0x"
+ << maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
+ << std::dec << "]";
+ return out.str();
+}
diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh
index 6210baa5c..90955447b 100644
--- a/src/mem/ruby/common/Address.hh
+++ b/src/mem/ruby/common/Address.hh
@@ -47,5 +47,6 @@ Addr shiftLowOrderBits(Addr addr, unsigned int number);
Addr getOffset(Addr addr);
Addr makeLineAddress(Addr addr);
Addr makeNextStrideAddress(Addr addr, int stride);
+std::string printAddress(Addr addr);
#endif // __MEM_RUBY_COMMON_ADDRESS_HH__
diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc
index 35850f61e..72c03457a 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -281,7 +281,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
void
MessageBuffer::reanalyzeMessages(Addr addr, Tick current_time)
{
- DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
+ DPRINTF(RubyQueue, "ReanalyzeMessages %#x\n", addr);
assert(m_stall_msg_map.count(addr) > 0);
//
@@ -315,7 +315,7 @@ MessageBuffer::reanalyzeAllMessages(Tick current_time)
void
MessageBuffer::stallMessage(Addr addr, Tick current_time)
{
- DPRINTF(RubyQueue, "Stalling due to %s\n", addr);
+ DPRINTF(RubyQueue, "Stalling due to %#x\n", addr);
assert(isReady(current_time));
assert(getOffset(addr) == 0);
MsgPtr message = m_prio_heap.front();
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index 416aea73b..00dfc6c64 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -55,21 +55,21 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
void
AbstractCacheEntry::setLocked(int context)
{
- DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", m_Address, context);
+ DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", m_Address, context);
m_locked = context;
}
void
AbstractCacheEntry::clearLocked()
{
- DPRINTF(RubyCache, "Clear Lock for addr: %x\n", m_Address);
+ DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", m_Address);
m_locked = -1;
}
bool
AbstractCacheEntry::isLocked(int context) const
{
- DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
+ DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
m_Address, m_locked, context);
return m_locked == context;
}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index be6438711..370781780 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -97,7 +97,7 @@ AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
msgVec->resize(m_in_ports, NULL);
m_waiting_buffers[addr] = msgVec;
}
- DPRINTF(RubyQueue, "stalling %s port %d addr %s\n", buf, m_cur_in_port,
+ DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
addr);
assert(m_in_ports > m_cur_in_port);
(*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc
index 350508671..c4c5b2faf 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -36,10 +36,10 @@ void
RubyRequest::print(ostream& out) const
{
out << "[RubyRequest: ";
- out << "LineAddress = " << m_LineAddress << " ";
- out << "PhysicalAddress = " << m_PhysicalAddress << " ";
+ out << hex << "LineAddress = 0x" << m_LineAddress << dec << " ";
+ out << hex << "PhysicalAddress = 0x" << m_PhysicalAddress << dec << " ";
out << "Type = " << m_Type << " ";
- out << "ProgramCounter = " << m_ProgramCounter << " ";
+ out << hex << "ProgramCounter = 0x" << m_ProgramCounter << dec << " ";
out << "AccessMode = " << m_AccessMode << " ";
out << "Size = " << m_Size << " ";
out << "Prefetch = " << m_Prefetch << " ";
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index a269d4f5b..b0e54ec99 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -163,7 +163,7 @@ CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr)
{
assert(address == makeLineAddress(address));
- DPRINTF(RubyCache, "address: %s\n", address);
+ DPRINTF(RubyCache, "address: %#x\n", address);
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
@@ -190,7 +190,7 @@ CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr)
{
assert(address == makeLineAddress(address));
- DPRINTF(RubyCache, "address: %s\n", address);
+ DPRINTF(RubyCache, "address: %#x\n", address);
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
@@ -218,10 +218,10 @@ CacheMemory::isTagPresent(Addr address) const
if (loc == -1) {
// We didn't find the tag
- DPRINTF(RubyCache, "No tag match for address: %s\n", address);
+ DPRINTF(RubyCache, "No tag match for address: %#x\n", address);
return false;
}
- DPRINTF(RubyCache, "address: %s found\n", address);
+ DPRINTF(RubyCache, "address: %#x found\n", address);
return true;
}
@@ -256,7 +256,7 @@ CacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch)
assert(address == makeLineAddress(address));
assert(!isTagPresent(address));
assert(cacheAvail(address));
- DPRINTF(RubyCache, "address: %s\n", address);
+ DPRINTF(RubyCache, "address: %#x\n", address);
// Find the first open slot
int64_t cacheSet = addressToCacheSet(address);
@@ -288,7 +288,7 @@ CacheMemory::deallocate(Addr address)
{
assert(address == makeLineAddress(address));
assert(isTagPresent(address));
- DPRINTF(RubyCache, "address: %s\n", address);
+ DPRINTF(RubyCache, "address: %#x\n", address);
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
@@ -417,7 +417,7 @@ CacheMemory::printData(ostream& out) const
void
CacheMemory::setLocked(Addr address, int context)
{
- DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
+ DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", address, context);
assert(address == makeLineAddress(address));
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
@@ -428,7 +428,7 @@ CacheMemory::setLocked(Addr address, int context)
void
CacheMemory::clearLocked(Addr address)
{
- DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
+ DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", address);
assert(address == makeLineAddress(address));
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
@@ -443,7 +443,7 @@ CacheMemory::isLocked(Addr address, int context)
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
- DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
+ DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
address, m_cache[cacheSet][loc]->m_locked, context);
return m_cache[cacheSet][loc]->isLocked(context);
}
@@ -582,7 +582,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
if (tagArray.tryAccess(addressToCacheSet(addr))) return true;
else {
DPRINTF(RubyResourceStalls,
- "Tag array stall on addr %s in set %d\n",
+ "Tag array stall on addr %#x in set %d\n",
addr, addressToCacheSet(addr));
numTagArrayStalls++;
return false;
@@ -591,7 +591,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
if (dataArray.tryAccess(addressToCacheSet(addr))) return true;
else {
DPRINTF(RubyResourceStalls,
- "Data array stall on addr %s in set %d\n",
+ "Data array stall on addr %#x in set %d\n",
addr, addressToCacheSet(addr));
numDataArrayStalls++;
return false;
diff --git a/src/mem/ruby/structures/DirectoryMemory.cc b/src/mem/ruby/structures/DirectoryMemory.cc
index 267c07174..8aad6f4fa 100644
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -114,7 +114,7 @@ AbstractEntry*
DirectoryMemory::lookup(Addr address)
{
assert(isPresent(address));
- DPRINTF(RubyCache, "Looking up address: %s\n", address);
+ DPRINTF(RubyCache, "Looking up address: %#x\n", address);
uint64_t idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
@@ -126,7 +126,7 @@ DirectoryMemory::allocate(Addr address, AbstractEntry *entry)
{
assert(isPresent(address));
uint64_t idx;
- DPRINTF(RubyCache, "Looking up address: %s\n", address);
+ DPRINTF(RubyCache, "Looking up address: %#x\n", address);
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc
index d12665ae9..ce6d36c04 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/Prefetcher.cc
@@ -135,7 +135,7 @@ Prefetcher::regStats()
void
Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
{
- DPRINTF(RubyPrefetcher, "Observed miss for %s\n", address);
+ DPRINTF(RubyPrefetcher, "Observed miss for %#x\n", address);
Addr line_addr = makeLineAddress(address);
numMissObserved++;
@@ -204,7 +204,7 @@ void
Prefetcher::observePfMiss(Addr address)
{
numPartialHits++;
- DPRINTF(RubyPrefetcher, "Observed partial hit for %s\n", address);
+ DPRINTF(RubyPrefetcher, "Observed partial hit for %#x\n", address);
issueNextPrefetch(address, NULL);
}
@@ -212,7 +212,7 @@ void
Prefetcher::observePfHit(Addr address)
{
numHits++;
- DPRINTF(RubyPrefetcher, "Observed hit for %s\n", address);
+ DPRINTF(RubyPrefetcher, "Observed hit for %#x\n", address);
issueNextPrefetch(address, NULL);
}
@@ -250,7 +250,7 @@ Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
// launch next prefetch
stream->m_address = line_addr;
stream->m_use_time = m_controller->curCycle();
- DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
+ DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
m_controller->enqueuePrefetch(line_addr, stream->m_type);
}
@@ -314,7 +314,7 @@ Prefetcher::initializeStream(Addr address, int stride,
// launch prefetch
numPrefetchRequested++;
- DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
+ DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
m_controller->enqueuePrefetch(line_addr, m_array[index].m_type);
}
diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc
index 454775178..3ad3911cb 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -404,7 +404,7 @@ RubySystem::functionalRead(PacketPtr pkt)
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
- DPRINTF(RubySystem, "Functional Read request for %s\n", address);
+ DPRINTF(RubySystem, "Functional Read request for %#x\n", address);
unsigned int num_ro = 0;
unsigned int num_rw = 0;
@@ -486,7 +486,7 @@ RubySystem::functionalWrite(PacketPtr pkt)
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
- DPRINTF(RubySystem, "Functional Write request for %s\n", addr);
+ DPRINTF(RubySystem, "Functional Write request for %#x\n", addr);
uint32_t M5_VAR_USED num_functional_writes = 0;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 815e270b6..aa4ac742a 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -443,7 +443,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
curTick(), m_version, "Seq",
llscSuccess ? "Done" : "SC_Failed", "", "",
- request_address, total_latency);
+ printAddress(request_address), total_latency);
// update the data unless it is a non-data-carrying flush
if (RubySystem::getWarmupEnabled()) {
@@ -610,7 +610,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
curTick(), m_version, "Seq", "Begin", "", "",
- msg->getPhysicalAddress(),
+ printAddress(msg->getPhysicalAddress()),
RubyRequestType_to_string(secondary_type));
// The Sequencer currently assesses instruction and data cache hit latency
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 07:49:47 +0000