diff options
Diffstat (limited to 'src/mem/ruby')
| -rw-r--r-- | src/mem/ruby/profiler/CacheProfiler.cc | 165 | ||||
| -rw-r--r-- | src/mem/ruby/profiler/CacheProfiler.hh | 88 | ||||
| -rw-r--r-- | src/mem/ruby/profiler/Profiler.hh | 1 | ||||
| -rw-r--r-- | src/mem/ruby/profiler/SConscript | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 143 | ||||
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 31 |
6 files changed, 100 insertions, 329 deletions
diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc deleted file mode 100644 index fdb4581bb..000000000 --- a/src/mem/ruby/profiler/CacheProfiler.cc +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "mem/ruby/profiler/CacheProfiler.hh" -#include "mem/ruby/profiler/Profiler.hh" -#include "mem/ruby/system/System.hh" - -using namespace std; - -CacheProfiler::CacheProfiler(const string& description) - : m_cacheRequestType(int(RubyRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM)) -{ - m_description = description; - - clearStats(); -} - -CacheProfiler::~CacheProfiler() -{ -} - -void -CacheProfiler::printStats(ostream& out) const -{ - out << "Cache Stats: " << m_description << endl; - string description = " " + m_description; - - out << description << "_total_misses: " << m_misses << endl; - out << description << "_total_demand_misses: " << m_demand_misses << endl; - out << description << "_total_prefetches: " << m_prefetches << endl; - out << description << "_total_sw_prefetches: " << m_sw_prefetches << endl; - out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl; - out << endl; - - int requests = 0; - - for (int i = 0; i < int(RubyRequestType_NUM); i++) { - requests += m_cacheRequestType[i]; - } - - for (int i = 0; i < int(GenericRequestType_NUM); i++) { - requests += m_genericRequestType[i]; - } - - assert(m_misses == requests); - - if (requests > 0) { - for (int i = 0; i < int(RubyRequestType_NUM); i++) { - if (m_cacheRequestType[i] > 0) { - out << description << "_request_type_" - << RubyRequestType_to_string(RubyRequestType(i)) - << ": " - << 100.0 * (double)m_cacheRequestType[i] / - (double)requests - << "%" << endl; - } - } - - for (int i = 0; i < int(GenericRequestType_NUM); i++) { - if (m_genericRequestType[i] > 0) { - out << description << "_request_type_" - << GenericRequestType_to_string(GenericRequestType(i)) - << ": " - << 100.0 * (double)m_genericRequestType[i] / - (double)requests - << "%" << endl; - } - } - - out << endl; - - for (int i = 0; i < RubyAccessMode_NUM; i++){ - if (m_accessModeTypeHistogram[i] > 0) { - out << description << "_access_mode_type_" - << (RubyAccessMode) i << ": " - << m_accessModeTypeHistogram[i] << " " - << 100.0 * m_accessModeTypeHistogram[i] / requests - << "%" << endl; - } - } - } - - out << endl; -} - -void -CacheProfiler::clearStats() -{ - for (int i = 0; i < int(RubyRequestType_NUM); i++) { - m_cacheRequestType[i] = 0; - } - for (int i = 0; i < int(GenericRequestType_NUM); i++) { - m_genericRequestType[i] = 0; - } - m_misses = 0; - m_demand_misses = 0; - m_prefetches = 0; - m_sw_prefetches = 0; - m_hw_prefetches = 0; - for (int i = 0; i < RubyAccessMode_NUM; i++) { - m_accessModeTypeHistogram[i] = 0; - } -} - -void -CacheProfiler::addCacheStatSample(RubyRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_cacheRequestType[requestType]++; - addStatSample(accessType, pfBit); -} - -void -CacheProfiler::addGenericStatSample(GenericRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_genericRequestType[requestType]++; - addStatSample(accessType, pfBit); -} - -void -CacheProfiler::addStatSample(RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_misses++; - - m_accessModeTypeHistogram[accessType]++; - if (pfBit == PrefetchBit_No) { - m_demand_misses++; - } else if (pfBit == PrefetchBit_Yes) { - m_prefetches++; - m_sw_prefetches++; - } else { - // must be L1_HW || L2_HW prefetch - m_prefetches++; - m_hw_prefetches++; - } -} diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh deleted file mode 100644 index c53db7ea8..000000000 --- a/src/mem/ruby/profiler/CacheProfiler.hh +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MEM_RUBY_PROFILER_CACHEPROFILER_HH__ -#define __MEM_RUBY_PROFILER_CACHEPROFILER_HH__ - -#include <iostream> -#include <string> -#include <vector> - -#include "mem/protocol/GenericRequestType.hh" -#include "mem/protocol/PrefetchBit.hh" -#include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/RubyRequestType.hh" -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/common/Histogram.hh" - -class CacheProfiler -{ - public: - CacheProfiler(const std::string& description); - ~CacheProfiler(); - - void printStats(std::ostream& out) const; - void clearStats(); - - void addCacheStatSample(RubyRequestType requestType, - RubyAccessMode type, - PrefetchBit pfBit); - - void addGenericStatSample(GenericRequestType requestType, - RubyAccessMode type, - PrefetchBit pfBit); - - void print(std::ostream& out) const; - - private: - // Private copy constructor and assignment operator - CacheProfiler(const CacheProfiler& obj); - CacheProfiler& operator=(const CacheProfiler& obj); - void addStatSample(RubyAccessMode type, PrefetchBit pfBit); - - std::string m_description; - int64 m_misses; - int64 m_demand_misses; - int64 m_prefetches; - int64 m_sw_prefetches; - int64 m_hw_prefetches; - int64 m_accessModeTypeHistogram[RubyAccessMode_NUM]; - - std::vector<int> m_cacheRequestType; - std::vector<int> m_genericRequestType; -}; - -inline std::ostream& -operator<<(std::ostream& out, const CacheProfiler& obj) -{ - obj.print(out); - out << std::flush; - return out; -} - -#endif // __MEM_RUBY_PROFILER_CACHEPROFILER_HH__ diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 02c37bd60..6bd9deee5 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -53,7 +53,6 @@ #include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/GenericMachineType.hh" -#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/RubyRequestType.hh" diff --git a/src/mem/ruby/profiler/SConscript b/src/mem/ruby/profiler/SConscript index 70082ad03..613c70aa0 100644 --- a/src/mem/ruby/profiler/SConscript +++ b/src/mem/ruby/profiler/SConscript @@ -37,7 +37,6 @@ SimObject('Profiler.py') Source('AccessTraceForAddress.cc') Source('AddressProfiler.cc') -Source('CacheProfiler.cc') Source('MemCntrlProfiler.cc') Source('Profiler.cc') Source('StoreTrace.cc') diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 81d73f5b4..f57c4c7ad 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -60,7 +60,6 @@ CacheMemory::CacheMemory(const Params *p) m_latency = p->latency; m_cache_assoc = p->assoc; m_policy = p->replacement_policy; - m_profiler_ptr = new CacheProfiler(name()); m_start_index_bit = p->start_index_bit; m_is_instruction_only_cache = p->is_icache; m_resource_stalls = p->resourceStalls; @@ -97,7 +96,6 @@ CacheMemory::~CacheMemory() { if (m_replacementPolicy_ptr != NULL) delete m_replacementPolicy_ptr; - delete m_profiler_ptr; for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { delete m_cache[i][j]; @@ -325,24 +323,6 @@ CacheMemory::setMRU(const Address& address) } void -CacheMemory::profileMiss(const RubyRequest& msg) -{ - m_profiler_ptr->addCacheStatSample(msg.getType(), - msg.getAccessMode(), - msg.getPrefetch()); -} - -void -CacheMemory::profileGenericRequest(GenericRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit) -{ - m_profiler_ptr->addGenericStatSample(requestType, - accessType, - pfBit); -} - -void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { uint64 warmedUpBlocks = 0; @@ -407,18 +387,6 @@ CacheMemory::printData(ostream& out) const } void -CacheMemory::clearStats() const -{ - m_profiler_ptr->clearStats(); -} - -void -CacheMemory::printStats(ostream& out) const -{ - m_profiler_ptr->printStats(out); -} - -void CacheMemory::setLocked(const Address& address, int context) { DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); @@ -453,63 +421,118 @@ CacheMemory::isLocked(const Address& address, int context) } void -CacheMemory::recordRequestType(CacheRequestType requestType) { - DPRINTF(RubyStats, "Recorded statistic: %s\n", - CacheRequestType_to_string(requestType)); - switch(requestType) { - case CacheRequestType_DataArrayRead: - numDataArrayReads++; - return; - case CacheRequestType_DataArrayWrite: - numDataArrayWrites++; - return; - case CacheRequestType_TagArrayRead: - numTagArrayReads++; - return; - case CacheRequestType_TagArrayWrite: - numTagArrayWrites++; - return; - default: - warn("CacheMemory access_type not found: %s", - CacheRequestType_to_string(requestType)); - } -} +CacheMemory::regStats() +{ + m_demand_hits + .name(name() + ".demand_hits") + .desc("Number of cache demand hits") + ; -void -CacheMemory::regStats() { - using namespace Stats; + m_demand_misses + .name(name() + ".demand_misses") + .desc("Number of cache demand misses") + ; + + m_demand_accesses + .name(name() + ".demand_accesses") + .desc("Number of cache demand accesses") + ; + + m_demand_accesses = m_demand_hits + m_demand_misses; + + m_sw_prefetches + .name(name() + ".total_sw_prefetches") + .desc("Number of software prefetches") + .flags(Stats::nozero) + ; + + m_hw_prefetches + .name(name() + ".total_hw_prefetches") + .desc("Number of hardware prefetches") + .flags(Stats::nozero) + ; + + m_prefetches + .name(name() + ".total_prefetches") + .desc("Number of prefetches") + .flags(Stats::nozero) + ; + + m_prefetches = m_sw_prefetches + m_hw_prefetches; + + m_accessModeType + .init(RubyRequestType_NUM) + .name(name() + ".access_mode") + .flags(Stats::pdf | Stats::total) + ; + for (int i = 0; i < RubyAccessMode_NUM; i++) { + m_accessModeType + .subname(i, RubyAccessMode_to_string(RubyAccessMode(i))) + .flags(Stats::nozero) + ; + } numDataArrayReads .name(name() + ".num_data_array_reads") .desc("number of data array reads") + .flags(Stats::nozero) ; numDataArrayWrites .name(name() + ".num_data_array_writes") .desc("number of data array writes") + .flags(Stats::nozero) ; numTagArrayReads .name(name() + ".num_tag_array_reads") .desc("number of tag array reads") + .flags(Stats::nozero) ; numTagArrayWrites .name(name() + ".num_tag_array_writes") .desc("number of tag array writes") + .flags(Stats::nozero) ; numTagArrayStalls .name(name() + ".num_tag_array_stalls") .desc("number of stalls caused by tag array") + .flags(Stats::nozero) ; numDataArrayStalls .name(name() + ".num_data_array_stalls") .desc("number of stalls caused by data array") + .flags(Stats::nozero) ; } +void +CacheMemory::recordRequestType(CacheRequestType requestType) +{ + DPRINTF(RubyStats, "Recorded statistic: %s\n", + CacheRequestType_to_string(requestType)); + switch(requestType) { + case CacheRequestType_DataArrayRead: + numDataArrayReads++; + return; + case CacheRequestType_DataArrayWrite: + numDataArrayWrites++; + return; + case CacheRequestType_TagArrayRead: + numTagArrayReads++; + return; + case CacheRequestType_TagArrayWrite: + numTagArrayWrites++; + return; + default: + warn("CacheMemory access_type not found: %s", + CacheRequestType_to_string(requestType)); + } +} + bool CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr) { @@ -520,14 +543,18 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr) if (res == CacheResourceType_TagArray) { if (tagArray.tryAccess(addressToCacheSet(addr))) return true; else { - DPRINTF(RubyResourceStalls, "Tag array stall on addr %s in set %d\n", addr, addressToCacheSet(addr)); + DPRINTF(RubyResourceStalls, + "Tag array stall on addr %s in set %d\n", + addr, addressToCacheSet(addr)); numTagArrayStalls++; return false; } } else if (res == CacheResourceType_DataArray) { if (dataArray.tryAccess(addressToCacheSet(addr))) return true; else { - DPRINTF(RubyResourceStalls, "Data array stall on addr %s in set %d\n", addr, addressToCacheSet(addr)); + DPRINTF(RubyResourceStalls, + "Data array stall on addr %s in set %d\n", + addr, addressToCacheSet(addr)); numDataArrayStalls++; return false; } diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 8aca250b3..db9e00e21 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -36,10 +36,8 @@ #include "base/statistics.hh" #include "mem/protocol/CacheResourceType.hh" #include "mem/protocol/CacheRequestType.hh" -#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/RubyRequest.hh" #include "mem/ruby/common/DataBlock.hh" -#include "mem/ruby/profiler/CacheProfiler.hh" #include "mem/ruby/recorder/CacheRecorder.hh" #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" @@ -100,34 +98,37 @@ class CacheMemory : public SimObject // Set this address to most recently used void setMRU(const Address& address); - void profileMiss(const RubyRequest & msg); - - void profileGenericRequest(GenericRequestType requestType, - RubyAccessMode accessType, - PrefetchBit pfBit); - void setLocked (const Address& addr, int context); void clearLocked (const Address& addr); bool isLocked (const Address& addr, int context); + // Print cache contents void print(std::ostream& out) const; void printData(std::ostream& out) const; - void clearStats() const; - void printStats(std::ostream& out) const; - - void recordRequestType(CacheRequestType requestType); void regStats(); + bool checkResourceAvailable(CacheResourceType res, Address addr); + void recordRequestType(CacheRequestType requestType); + + public: + Stats::Scalar m_demand_hits; + Stats::Scalar m_demand_misses; + Stats::Formula m_demand_accesses; + + Stats::Scalar m_sw_prefetches; + Stats::Scalar m_hw_prefetches; + Stats::Formula m_prefetches; + + Stats::Vector m_accessModeType; Stats::Scalar numDataArrayReads; Stats::Scalar numDataArrayWrites; Stats::Scalar numTagArrayReads; Stats::Scalar numTagArrayWrites; - bool checkResourceAvailable(CacheResourceType res, Address addr); - Stats::Scalar numTagArrayStalls; Stats::Scalar numDataArrayStalls; + private: // convert a Address to its location in the cache Index addressToCacheSet(const Address& address) const; @@ -156,8 +157,6 @@ class CacheMemory : public SimObject AbstractReplacementPolicy *m_replacementPolicy_ptr; - CacheProfiler* m_profiler_ptr; - BankedArray dataArray; BankedArray tagArray; |