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-rw-r--r--src/mem/ruby/common/Address.hh1
-rw-r--r--src/mem/ruby/profiler/AddressProfiler.hh4
-rw-r--r--src/mem/ruby/profiler/Profiler.hh1
-rw-r--r--src/mem/ruby/structures/CacheMemory.cc4
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh4
-rw-r--r--src/mem/ruby/structures/PerfectCacheMemory.hh5
-rw-r--r--src/mem/ruby/structures/PersistentTable.hh4
-rw-r--r--src/mem/ruby/structures/RubyMemoryControl.hh2
-rw-r--r--src/mem/ruby/structures/TBETable.hh4
-rw-r--r--src/mem/ruby/system/CacheRecorder.hh1
-rw-r--r--src/mem/ruby/system/DMASequencer.hh2
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
-rw-r--r--src/mem/ruby/system/RubySystem.hh6
-rw-r--r--src/mem/ruby/system/Sequencer.cc6
-rw-r--r--src/mem/ruby/system/Sequencer.hh4
15 files changed, 24 insertions, 26 deletions
diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh
index 90955447b..ded6f6f12 100644
--- a/src/mem/ruby/common/Address.hh
+++ b/src/mem/ruby/common/Address.hh
@@ -33,7 +33,6 @@
#include <iomanip>
#include <iostream>
-#include "base/hashmap.hh"
#include "base/types.hh"
const uint32_t ADDRESS_WIDTH = 64; // address width in bytes
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index ebd44080b..9f12415c5 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -30,8 +30,8 @@
#define __MEM_RUBY_PROFILER_ADDRESSPROFILER_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/common/Address.hh"
@@ -44,7 +44,7 @@ class Set;
class AddressProfiler
{
public:
- typedef m5::hash_map<Addr, AccessTraceForAddress> AddressMap;
+ typedef std::unordered_map<Addr, AccessTraceForAddress> AddressMap;
public:
AddressProfiler(int num_of_sequencers, Profiler *profiler);
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 146beadd6..7e45e8aeb 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -50,7 +50,6 @@
#include <vector>
#include "base/callback.hh"
-#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/PrefetchBit.hh"
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index 6e4022ea6..a8a3ba949 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -113,7 +113,7 @@ CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const
{
assert(tag == makeLineAddress(tag));
// search the set for the tags
- m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
+ auto it = m_tag_index.find(tag);
if (it != m_tag_index.end())
if (m_cache[cacheSet][it->second]->m_Permission !=
AccessPermission_NotPresent)
@@ -129,7 +129,7 @@ CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet,
{
assert(tag == makeLineAddress(tag));
// search the set for the tags
- m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
+ auto it = m_tag_index.find(tag);
if (it != m_tag_index.end())
return it->second;
return -1; // Not found
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 7ce674e61..72805b32b 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -31,9 +31,9 @@
#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
#include <string>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/CacheResourceType.hh"
@@ -168,7 +168,7 @@ class CacheMemory : public SimObject
// The first index is the # of cache lines.
// The second index is the the amount associativity.
- m5::hash_map<Addr, int> m_tag_index;
+ std::unordered_map<Addr, int> m_tag_index;
std::vector<std::vector<AbstractCacheEntry*> > m_cache;
AbstractReplacementPolicy *m_replacementPolicy_ptr;
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 2b8b87628..61d5e1244 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -29,7 +29,8 @@
#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/common/Address.hh"
@@ -87,7 +88,7 @@ class PerfectCacheMemory
PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
// Data Members (m_prefix)
- m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
+ std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
};
template<class ENTRY>
diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh
index a4604fce8..e5296d1e8 100644
--- a/src/mem/ruby/structures/PersistentTable.hh
+++ b/src/mem/ruby/structures/PersistentTable.hh
@@ -30,8 +30,8 @@
#define __MEM_RUBY_STRUCTURES_PERSISTENTTABLE_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/MachineID.hh"
@@ -77,7 +77,7 @@ class PersistentTable
PersistentTable& operator=(const PersistentTable& obj);
// Data Members (m_prefix)
- typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap;
+ typedef std::unordered_map<Addr, PersistentTableEntry> AddressMap;
AddressMap m_map;
};
diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh
index f5f31458b..75fe71dfb 100644
--- a/src/mem/ruby/structures/RubyMemoryControl.hh
+++ b/src/mem/ruby/structures/RubyMemoryControl.hh
@@ -60,7 +60,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
PortID idx = InvalidPortID);
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
void wakeup();
void setDescription(const std::string& name) { m_description = name; };
diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh
index 4a24a5b13..a39c5af2e 100644
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -30,8 +30,8 @@
#define __MEM_RUBY_STRUCTURES_TBETABLE_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
template<class ENTRY>
@@ -63,7 +63,7 @@ class TBETable
TBETable& operator=(const TBETable& obj);
// Data Members (m_prefix)
- m5::hash_map<Addr, ENTRY> m_map;
+ std::unordered_map<Addr, ENTRY> m_map;
private:
int m_number_of_TBEs;
diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh
index 44110cf9f..822b370e8 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -37,7 +37,6 @@
#include <vector>
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index f9d1b630e..1d5451f6e 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -108,7 +108,7 @@ class DMASequencer : public MemObject
// A pointer to the controller is needed for atomic support.
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
uint32_t getId() { return m_version; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/* SLICC callback */
void dataCallback(const DataBlock & dblk);
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index cbcc678d3..98fab8c4e 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -161,7 +161,7 @@ class RubyPort : public MemObject
//
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
uint32_t getId() { return m_version; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
protected:
void ruby_hit_callback(PacketPtr pkt);
diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh
index 7026f6756..23974e924 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -94,9 +94,9 @@ class RubySystem : public ClockedObject
void resetStats();
void memWriteback();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+ void drainResume() override;
void process();
void startup();
bool functionalRead(Packet *ptr);
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index aa4ac742a..26db6b6f8 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -634,10 +634,10 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
template <class KEY, class VALUE>
std::ostream &
-operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
+operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
{
- typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
- typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
+ auto i = map.begin();
+ auto end = map.end();
out << "[";
for (; i != end; ++i)
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 4716aa653..47af7ea1e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -30,8 +30,8 @@
#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/SequencerRequestType.hh"
@@ -185,7 +185,7 @@ class Sequencer : public RubyPort
Cycles m_data_cache_hit_latency;
Cycles m_inst_cache_hit_latency;
- typedef m5::hash_map<Addr, SequencerRequest*> RequestTable;
+ typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
RequestTable m_writeRequestTable;
RequestTable m_readRequestTable;
// Global outstanding request count, across all request tables
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 20:04:13 +0000