3 files changed, 7 insertions, 29 deletions

diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 1769c51fd..8fd68be7c 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -45,14 +45,14 @@
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/ruby/system/RubyPort.hh"
+#include "sim/system.hh"
 
 RubyPort::RubyPort(const Params *p)
     : MemObject(p), m_version(p->version), m_controller(NULL),
       m_mandatory_q_ptr(NULL),
       pio_port(csprintf("%s-pio-port", name()), this),
       m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
-      physMemPort(csprintf("%s-physMemPort", name()), this),
-      drainEvent(NULL), physmem(p->physmem), ruby_system(p->ruby_system),
+      drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
       waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
 {
     assert(m_version != -1);
@@ -84,10 +84,6 @@ RubyPort::getMasterPort(const std::string &if_name, int idx)
         return pio_port;
     }
 
-    if (if_name == "physMemPort") {
-        return physMemPort;
-    }
-
     // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
     // port
     if (if_name != "master") {
@@ -471,7 +467,7 @@ RubyPort::M5Port::recvFunctional(PacketPtr pkt)
         // The following command performs the real functional access.
         // This line should be removed once Ruby supplies the official version
         // of data.
-        ruby_port->physMemPort.sendFunctional(pkt);
+        ruby_port->system->physmem->doFunctionalAccess(pkt);
     }
 
     // turn packet around to go back to requester if response expected
@@ -568,10 +564,6 @@ RubyPort::getDrainCount(Event *de)
         count += pio_port.drain(de);
         DPRINTF(Config, "count after pio check %d\n", count);
     }
-    if (physMemPort.isConnected()) {
-        count += physMemPort.drain(de);
-        DPRINTF(Config, "count after physmem check %d\n", count);
-    }
 
     for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
         count += (*p)->drain(de);
@@ -654,7 +646,7 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt)
     DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
 
     if (accessPhysMem) {
-        ruby_port->physMemPort.sendAtomic(pkt);
+        ruby_port->system->physmem->doAtomicAccess(pkt);
     } else if (needsResponse) {
         pkt->makeResponse();
     }
@@ -696,18 +688,7 @@ RubyPort::M5Port::getAddrRanges()
 bool
 RubyPort::M5Port::isPhysMemAddress(Addr addr)
 {
-    AddrRangeList physMemAddrList =
-        ruby_port->physMemPort.getSlavePort().getAddrRanges();
-    for (AddrRangeIter iter = physMemAddrList.begin();
-         iter != physMemAddrList.end();
-         iter++) {
-        if (addr >= iter->start && addr <= iter->end) {
-            DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n",
-                    iter->start, iter->end);
-            return true;
-        }
-    }
-    return false;
+    return ruby_port->system->isMemory(addr);
 }
 
 unsigned
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index d97f6e69e..553614021 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -175,8 +175,6 @@ class RubyPort : public MemObject
     uint16_t m_port_id;
     uint64_t m_request_cnt;
 
-    PioPort physMemPort;
-
     /** Vector of M5 Ports attached to this Ruby port. */
     typedef std::vector<M5Port*>::iterator CpuPortIter;
     std::vector<M5Port*> slave_ports;
@@ -184,8 +182,8 @@ class RubyPort : public MemObject
 
     Event *drainEvent;
 
-    PhysicalMemory* physmem;
     RubySystem* ruby_system;
+    System* system;
 
     //
     // Based on similar code in the M5 bus.  Stores pointers to those ports
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index b1e17e052..02686d33f 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -38,13 +38,12 @@ class RubyPort(MemObject):
     master = VectorMasterPort("CPU master port")
     version = Param.Int(0, "")
     pio_port = MasterPort("Ruby_pio_port")
-    physmem = Param.PhysicalMemory("")
-    physMemPort = MasterPort("port to physical memory")
     using_ruby_tester = Param.Bool(False, "")
     using_network_tester = Param.Bool(False, "")
     access_phys_mem = Param.Bool(True,
         "should the rubyport atomically update phys_mem")
     ruby_system = Param.RubySystem("")
+    system = Param.System(Parent.any, "system object")
 
 class RubyPortProxy(RubyPort):
     type = 'RubyPortProxy'