diff options
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/buffers/MessageBuffer.cc | 2 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/NetworkMessage.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/system/DMASequencer.cc | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc index 298fdb3c3..b63b07976 100644 --- a/src/mem/ruby/buffers/MessageBuffer.cc +++ b/src/mem/ruby/buffers/MessageBuffer.cc @@ -160,7 +160,7 @@ MessageBuffer::enqueue(MsgPtr message, Cycles delta) Tick current_time = m_sender->clockEdge(); Tick arrival_time = 0; - if (!RubySystem::getRandomization() || (m_randomization == false)) { + if (!RubySystem::getRandomization() || !m_randomization) { // No randomization arrival_time = current_time + delta * m_sender->clockPeriod(); } else { diff --git a/src/mem/ruby/slicc_interface/NetworkMessage.hh b/src/mem/ruby/slicc_interface/NetworkMessage.hh index 03d05d15d..10d78251a 100644 --- a/src/mem/ruby/slicc_interface/NetworkMessage.hh +++ b/src/mem/ruby/slicc_interface/NetworkMessage.hh @@ -60,7 +60,7 @@ class NetworkMessage : public Message const NetDest& getInternalDestination() const { - if (m_internal_dest_valid == false) + if (!m_internal_dest_valid) return getDestination(); return m_internal_dest; @@ -69,7 +69,7 @@ class NetworkMessage : public Message NetDest& getInternalDestination() { - if (m_internal_dest_valid == false) { + if (!m_internal_dest_valid) { m_internal_dest = getDestination(); m_internal_dest_valid = true; } diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index 469d19be6..9b0157b45 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -94,7 +94,7 @@ DMASequencer::makeRequest(PacketPtr pkt) void DMASequencer::issueNext() { - assert(m_is_busy == true); + assert(m_is_busy); active_request.bytes_completed = active_request.bytes_issued; if (active_request.len == active_request.bytes_completed) { // @@ -144,12 +144,12 @@ DMASequencer::issueNext() void DMASequencer::dataCallback(const DataBlock & dblk) { - assert(m_is_busy == true); + assert(m_is_busy); int len = active_request.bytes_issued - active_request.bytes_completed; int offset = 0; if (active_request.bytes_completed == 0) offset = active_request.start_paddr & m_data_block_mask; - assert(active_request.write == false); + assert(!active_request.write); if (active_request.data != NULL) { memcpy(&active_request.data[active_request.bytes_completed], dblk.getData(offset, len), len); |