diff options
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/common/Address.cc | 16 | ||||
-rw-r--r-- | src/mem/ruby/common/Address.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/structures/Prefetcher.cc | 23 | ||||
-rw-r--r-- | src/mem/ruby/structures/Prefetcher.hh | 6 | ||||
-rw-r--r-- | src/mem/ruby/structures/RubyPrefetcher.py | 3 |
5 files changed, 25 insertions, 25 deletions
diff --git a/src/mem/ruby/common/Address.cc b/src/mem/ruby/common/Address.cc index eb234f46e..5d9fa49e5 100644 --- a/src/mem/ruby/common/Address.cc +++ b/src/mem/ruby/common/Address.cc @@ -26,8 +26,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/isa_traits.hh" -#include "config/the_isa.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/system/System.hh" @@ -136,20 +134,6 @@ Address::operator=(const Address& obj) return *this; } -void -Address::makePageAddress() -{ - m_address = maskLowOrderBits(TheISA::PageShift); -} - -Address -page_address(const Address& addr) -{ - Address temp = addr; - temp.makePageAddress(); - return temp; -} - Address next_stride_address(const Address& addr, int stride) { diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index feb8741c9..d47ff9ac5 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -69,7 +69,6 @@ class Address physical_address_t getLineAddress() const; physical_address_t getOffset() const; void makeLineAddress(); - void makePageAddress(); void makeNextStrideAddress(int stride); int64 memoryModuleIndex() const; @@ -201,7 +200,6 @@ Address::shiftLowOrderBits(unsigned int number) const } Address next_stride_address(const Address& addr, int stride); -Address page_address(const Address& addr); __hash_namespace_begin template <> struct hash<Address> diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc index 05a1d8e62..306174c2c 100644 --- a/src/mem/ruby/structures/Prefetcher.cc +++ b/src/mem/ruby/structures/Prefetcher.cc @@ -45,7 +45,8 @@ Prefetcher::Prefetcher(const Params *p) m_unit_filter(p->unit_filter, Address(0)), m_negative_filter(p->unit_filter, Address(0)), m_nonunit_filter(p->nonunit_filter, Address(0)), - m_prefetch_cross_pages(p->cross_page) + m_prefetch_cross_pages(p->cross_page), + m_page_shift(p->sys->getPageShift()) { assert(m_num_streams > 0); assert(m_num_startup_pfs <= MAX_PF_INFLIGHT); @@ -231,12 +232,12 @@ Prefetcher::issueNextPrefetch(const Address &address, PrefetchEntry *stream) } // extend this prefetching stream by 1 (or more) - Address page_addr = page_address(stream->m_address); + Address page_addr = pageAddress(stream->m_address); Address line_addr = next_stride_address(stream->m_address, stream->m_stride); // possibly stop prefetching at page boundaries - if (page_addr != page_address(line_addr)) { + if (page_addr != pageAddress(line_addr)) { numPagesCrossed++; if (!m_prefetch_cross_pages) { // Deallocate the stream since we are not prefetching @@ -295,7 +296,7 @@ Prefetcher::initializeStream(const Address& address, int stride, mystream->m_type = type; // create a number of initial prefetches for this stream - Address page_addr = page_address(mystream->m_address); + Address page_addr = pageAddress(mystream->m_address); Address line_addr = line_address(mystream->m_address); Address prev_addr = line_addr; @@ -303,7 +304,7 @@ Prefetcher::initializeStream(const Address& address, int stride, for (int k = 0; k < m_num_startup_pfs; k++) { line_addr = next_stride_address(line_addr, stride); // possibly stop prefetching at page boundaries - if (page_addr != page_address(line_addr)) { + if (page_addr != pageAddress(line_addr)) { numPagesCrossed++; if (!m_prefetch_cross_pages) { // deallocate this stream prefetcher @@ -382,11 +383,11 @@ Prefetcher::accessNonunitFilter(const Address& address, int *stride, alloc = false; /// look for non-unit strides based on a (user-defined) page size - Address page_addr = page_address(address); + Address page_addr = pageAddress(address); Address line_addr = line_address(address); for (uint32_t i = 0; i < m_num_nonunit_filters; i++) { - if (page_address(m_nonunit_filter[i]) == page_addr) { + if (pageAddress(m_nonunit_filter[i]) == page_addr) { // hit in the non-unit filter // compute the actual stride (for this reference) int delta = line_addr.getAddress() - m_nonunit_filter[i].getAddress(); @@ -467,3 +468,11 @@ Prefetcher::print(std::ostream& out) const << m_array[i].m_use_time << std::endl; } } + +Address +Prefetcher::pageAddress(const Address& addr) const +{ + Address temp = addr; + temp.maskLowOrderBits(m_page_shift); + return temp; +} diff --git a/src/mem/ruby/structures/Prefetcher.hh b/src/mem/ruby/structures/Prefetcher.hh index 2bc7d812e..6ed945b9e 100644 --- a/src/mem/ruby/structures/Prefetcher.hh +++ b/src/mem/ruby/structures/Prefetcher.hh @@ -41,6 +41,7 @@ #include "mem/ruby/system/System.hh" #include "params/Prefetcher.hh" #include "sim/sim_object.hh" +#include "sim/system.hh" #define MAX_PF_INFLIGHT 8 @@ -139,6 +140,9 @@ class Prefetcher : public SimObject bool accessNonunitFilter(const Address& address, int *stride, bool &alloc); + /// determine the page aligned address + Address pageAddress(const Address& addr) const; + //! number of prefetch streams available uint32_t m_num_streams; //! an array of the active prefetch streams @@ -187,6 +191,8 @@ class Prefetcher : public SimObject AbstractController *m_controller; + const Addr m_page_shift; + //! Count of accesses to the prefetcher Stats::Scalar numMissObserved; //! Count of prefetch streams allocated diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py index a02b11696..18bb3dc69 100644 --- a/src/mem/ruby/structures/RubyPrefetcher.py +++ b/src/mem/ruby/structures/RubyPrefetcher.py @@ -27,7 +27,9 @@ # Authors: Nilay Vaish from m5.SimObject import SimObject +from System import System from m5.params import * +from m5.proxy import * class Prefetcher(SimObject): type = 'Prefetcher' @@ -45,3 +47,4 @@ class Prefetcher(SimObject): num_startup_pfs = Param.UInt32(1, "") cross_page = Param.Bool(False, """True if prefetched address can be on a page different from the observed address""") + sys = Param.System(Parent.any, "System this prefetcher belongs to") |