diff options
Diffstat (limited to 'src/mem/ruby')
-rw-r--r-- | src/mem/ruby/network/MessageBuffer.hh | 10 | ||||
-rw-r--r-- | src/mem/ruby/network/Network.hh | 8 | ||||
-rw-r--r-- | src/mem/ruby/network/dummy_port.hh | 59 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 5 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 52 | ||||
-rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 6 |
7 files changed, 100 insertions, 44 deletions
diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh index 69a0fb33e..4e85ac413 100644 --- a/src/mem/ruby/network/MessageBuffer.hh +++ b/src/mem/ruby/network/MessageBuffer.hh @@ -43,10 +43,12 @@ #include "base/trace.hh" #include "debug/RubyQueue.hh" +#include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Consumer.hh" +#include "mem/ruby/network/dummy_port.hh" #include "mem/ruby/slicc_interface/Message.hh" -#include "mem/packet.hh" #include "params/MessageBuffer.hh" #include "sim/sim_object.hh" @@ -120,6 +122,12 @@ class MessageBuffer : public SimObject void setIncomingLink(int link_id) { m_input_link_id = link_id; } void setVnet(int net) { m_vnet_id = net; } + Port & + getPort(const std::string &, PortID idx=InvalidPortID) override + { + return RubyDummyPort::instance(); + } + void regStats(); // Function for figuring out if any of the messages in the buffer need diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index 7f5ed2aae..4e9791824 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -60,11 +60,13 @@ #include "base/addr_range.hh" #include "base/types.hh" #include "mem/packet.hh" +#include "mem/port.hh" #include "mem/protocol/LinkDirection.hh" #include "mem/protocol/MessageSizeType.hh" #include "mem/ruby/common/MachineID.hh" #include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/Topology.hh" +#include "mem/ruby/network/dummy_port.hh" #include "params/RubyNetwork.hh" #include "sim/clocked_object.hh" @@ -132,6 +134,12 @@ class Network : public ClockedObject */ NodeID addressToNodeID(Addr addr, MachineType mtype); + Port & + getPort(const std::string &, PortID idx=InvalidPortID) override + { + return RubyDummyPort::instance(); + } + protected: // Private copy constructor and assignment operator Network(const Network& obj); diff --git a/src/mem/ruby/network/dummy_port.hh b/src/mem/ruby/network/dummy_port.hh new file mode 100644 index 000000000..ca1ef4155 --- /dev/null +++ b/src/mem/ruby/network/dummy_port.hh @@ -0,0 +1,59 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __MEM_RUBY_NETWORK_DUMMY_PORT_HH__ +#define __MEM_RUBY_NETWORK_DUMMY_PORT_HH__ + +#include "mem/port.hh" + +class RubyDummyPort : public Port +{ + public: + RubyDummyPort() : Port("DummyPort", -1) {} + + void + bind(Port &peer) override + { + // No need to connect anything here currently. MessageBuffer + // port connections only serve to print the connections in + // the config output. + // TODO: Add real ports to MessageBuffers and use MemObject connect + // code below to bind MessageBuffer senders and receivers + } + void unbind() override {} + + static RubyDummyPort & + instance() + { + static RubyDummyPort dummy; + return dummy; + } +}; + +#endif //__MEM_RUBY_NETWORK_DUMMY_PORT_HH__ diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 1327eccfb..fa1c936b7 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -229,9 +229,8 @@ AbstractController::isBlocked(Addr addr) return (m_block_map.count(addr) > 0); } -BaseMasterPort & -AbstractController::getMasterPort(const std::string &if_name, - PortID idx) +Port & +AbstractController::getPort(const std::string &if_name, PortID idx) { return memoryPort; } diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 35cd3d2a5..5e39a28d2 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer virtual void initNetQueues() = 0; /** A function used to return the port associated with this bus object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 84a70c0f1..795b473c7 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -87,53 +87,37 @@ RubyPort::init() m_mandatory_q_ptr = m_controller->getMandatoryQueue(); } -BaseMasterPort & -RubyPort::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyPort::getPort(const std::string &if_name, PortID idx) { if (if_name == "mem_master_port") { return memMasterPort; - } - - if (if_name == "pio_master_port") { + } else if (if_name == "pio_master_port") { return pioMasterPort; - } - - // used by the x86 CPUs to connect the interrupt PIO and interrupt slave - // port - if (if_name != "master") { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } else { + } else if (if_name == "mem_slave_port") { + return memSlavePort; + } else if (if_name == "pio_slave_port") { + return pioSlavePort; + } else if (if_name == "master") { + // used by the x86 CPUs to connect the interrupt PIO and interrupt + // slave port if (idx >= static_cast<PortID>(master_ports.size())) { - panic("RubyPort::getMasterPort: unknown index %d\n", idx); + panic("RubyPort::getPort master: unknown index %d\n", idx); } return *master_ports[idx]; - } -} - -BaseSlavePort & -RubyPort::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "mem_slave_port") { - return memSlavePort; - } - - if (if_name == "pio_slave_port") - return pioSlavePort; - - // used by the CPUs to connect the caches to the interconnect, and - // for the x86 case also the interrupt master - if (if_name != "slave") { - // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); - } else { + } else if (if_name == "slave") { + // used by the CPUs to connect the caches to the interconnect, and + // for the x86 case also the interrupt master if (idx >= static_cast<PortID>(slave_ports.size())) { - panic("RubyPort::getSlavePort: unknown index %d\n", idx); + panic("RubyPort::getPort slave: unknown index %d\n", idx); } return *slave_ports[idx]; } + + // pass it along to our super class + return MemObject::getPort(if_name, idx); } RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 146443282..922b3a973 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -148,10 +148,8 @@ class RubyPort : public MemObject void init() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; |