1 files changed, 16 insertions, 1 deletions
diff --git a/src/mem/simple_dram.hh b/src/mem/simple_dram.hh
index 6521c6768..920dcf33a 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/simple_dram.hh
@@ -265,8 +265,9 @@ class SimpleDRAM : public AbstractMemory
      * world requestor.
      *
      * @param pkt The packet from the outside world
+     * @param static_latency Static latency to add before sending the packet
      */
-    void accessAndRespond(PacketPtr pkt);
+    void accessAndRespond(PacketPtr pkt, Tick static_latency);
 
     /**
      * Address decoder to figure out physical mapping onto ranks,
@@ -410,6 +411,20 @@ class SimpleDRAM : public AbstractMemory
     Enums::PageManage pageMgmt;
 
     /**
+     * Pipeline latency of the controller frontend. The frontend
+     * contribution is added to writes (that complete when they are in
+     * the write buffer) and reads that are serviced the write buffer.
+     */
+    const Tick frontendLatency;
+
+    /**
+     * Pipeline latency of the backend and PHY. Along with the
+     * frontend contribution, this latency is added to reads serviced
+     * by the DRAM.
+     */
+    const Tick backendLatency;
+
+    /**
      * Till when has the main data bus been spoken for already?
      */
     Tick busBusyUntil;