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path: root/src/mem/slicc/ast/OutPortDeclAST.py
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Diffstat (limited to 'src/mem/slicc/ast/OutPortDeclAST.py')
-rw-r--r--src/mem/slicc/ast/OutPortDeclAST.py4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mem/slicc/ast/OutPortDeclAST.py b/src/mem/slicc/ast/OutPortDeclAST.py
index a387f6d91..39795ef7e 100644
--- a/src/mem/slicc/ast/OutPortDeclAST.py
+++ b/src/mem/slicc/ast/OutPortDeclAST.py
@@ -25,8 +25,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from m5.util import code_formatter
-
from slicc.ast.DeclAST import DeclAST
from slicc.ast.TypeAST import TypeAST
from slicc.symbols import Var
@@ -45,7 +43,7 @@ class OutPortDeclAST(DeclAST):
return "[OutPortDecl: %r]" % self.ident
def generate(self):
- code = code_formatter(newlines=False)
+ code = self.slicc.codeFormatter(newlines=False)
queue_type = self.var_expr.generate(code)
if not queue_type.isOutPort: