diff options
Diffstat (limited to 'src/mem/slicc')
| -rw-r--r-- | src/mem/slicc/ast/StateDeclAST.py | 79 | ||||
| -rw-r--r-- | src/mem/slicc/ast/TypeFieldEnumAST.py | 9 | ||||
| -rw-r--r-- | src/mem/slicc/ast/TypeFieldStateAST.py | 61 | ||||
| -rw-r--r-- | src/mem/slicc/ast/__init__.py | 2 | ||||
| -rw-r--r-- | src/mem/slicc/parser.py | 20 | ||||
| -rw-r--r-- | src/mem/slicc/symbols/StateMachine.py | 13 | ||||
| -rw-r--r-- | src/mem/slicc/symbols/Type.py | 40 |
7 files changed, 218 insertions, 6 deletions
diff --git a/src/mem/slicc/ast/StateDeclAST.py b/src/mem/slicc/ast/StateDeclAST.py new file mode 100644 index 000000000..a1bbd74ae --- /dev/null +++ b/src/mem/slicc/ast/StateDeclAST.py @@ -0,0 +1,79 @@ +# Copyright (c) 2011 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from slicc.ast.DeclAST import DeclAST +from slicc.symbols import Func, Type + +class StateDeclAST(DeclAST): + def __init__(self, slicc, type_ast, pairs, states): + super(StateDeclAST, self).__init__(slicc, pairs) + + self.type_ast = type_ast + self.states = states + + def __repr__(self): + return "[StateDecl: %s]" % (self.type_ast) + + def files(self, parent=None): + if "external" in self: + return set() + + if parent: + ident = "%s_%s" % (parent, self.type_ast.ident) + else: + ident = self.type_ast.ident + s = set(("%s.hh" % ident, "%s.cc" % ident)) + return s + + def generate(self): + ident = str(self.type_ast) + + # Make the new type + t = Type(self.symtab, ident, self.location, self.pairs, + self.state_machine) + self.symtab.newSymbol(t) + + # Add all of the states of the type to it + for state in self.states: + state.generate(t) + + # Add the implicit State_to_string method - FIXME, this is a bit dirty + func_id = "%s_to_string" % t.c_ident + + pairs = { "external" : "yes" } + func = Func(self.symtab, func_id, self.location, + self.symtab.find("std::string", Type), [ t ], [], "", + pairs, None) + self.symtab.newSymbol(func) + + # Add the State_to_permission method + func_id = "%s_to_permission" % t.c_ident + + pairs = { "external" : "yes" } + func = Func(self.symtab, func_id, self.location, + self.symtab.find("AccessPermission", Type), [ t ], [], "", + pairs, None) + self.symtab.newSymbol(func) diff --git a/src/mem/slicc/ast/TypeFieldEnumAST.py b/src/mem/slicc/ast/TypeFieldEnumAST.py index 138fff793..398604550 100644 --- a/src/mem/slicc/ast/TypeFieldEnumAST.py +++ b/src/mem/slicc/ast/TypeFieldEnumAST.py @@ -39,6 +39,9 @@ class TypeFieldEnumAST(TypeFieldAST): return "[TypeFieldEnum: %r]" % self.field_id def generate(self, type): + if str(type) == "State": + self.error("States must in a State Declaration, not a normal enum.") + # Add enumeration if not type.enumAdd(self.field_id, self.pairs_ast.pairs): self.error("Duplicate enumeration: %s:%s" % (type, self.field_id)) @@ -46,12 +49,6 @@ class TypeFieldEnumAST(TypeFieldAST): # Fill machine info machine = self.symtab.state_machine - if str(type) == "State": - if not machine: - self.error("State declaration not part of a machine.") - s = State(self.symtab, self.field_id, self.location, self.pairs) - machine.addState(s) - if str(type) == "Event": if not machine: self.error("Event declaration not part of a machine.") diff --git a/src/mem/slicc/ast/TypeFieldStateAST.py b/src/mem/slicc/ast/TypeFieldStateAST.py new file mode 100644 index 000000000..aafa241dd --- /dev/null +++ b/src/mem/slicc/ast/TypeFieldStateAST.py @@ -0,0 +1,61 @@ +# Copyright (c) 2011 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from slicc.ast.TypeFieldAST import TypeFieldAST +from slicc.symbols import Event, State + +class TypeFieldStateAST(TypeFieldAST): + def __init__(self, slicc, field_id, perm_ast, pairs_ast): + super(TypeFieldStateAST, self).__init__(slicc, pairs_ast) + + self.field_id = field_id + self.perm_ast = perm_ast + if not (perm_ast.type_ast.ident == "AccessPermission"): + self.error("AccessPermission enum value must be specified") + self.pairs_ast = pairs_ast + + def __repr__(self): + return "[TypeFieldState: %r]" % self.field_id + + def generate(self, type): + if not str(type) == "State": + self.error("State Declaration must be of type State.") + + # Add enumeration + if not type.enumAdd(self.field_id, self.pairs_ast.pairs): + self.error("Duplicate enumeration: %s:%s" % (type, self.field_id)) + + # Fill machine info + machine = self.symtab.state_machine + + if not machine: + self.error("State declaration not part of a machine.") + s = State(self.symtab, self.field_id, self.location, self.pairs) + machine.addState(s) + + type.statePermPairAdd(s, self.perm_ast.value) + + diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py index 4af6c2036..c0f54a9a3 100644 --- a/src/mem/slicc/ast/__init__.py +++ b/src/mem/slicc/ast/__init__.py @@ -61,6 +61,7 @@ from slicc.ast.PairListAST import * from slicc.ast.PeekStatementAST import * from slicc.ast.ReturnStatementAST import * from slicc.ast.StallAndWaitStatementAST import * +from slicc.ast.StateDeclAST import * from slicc.ast.StatementAST import * from slicc.ast.StatementListAST import * from slicc.ast.StaticCastAST import * @@ -71,6 +72,7 @@ from slicc.ast.TypeFieldAST import * from slicc.ast.TypeFieldEnumAST import * from slicc.ast.TypeFieldMemberAST import * from slicc.ast.TypeFieldMethodAST import * +from slicc.ast.TypeFieldStateAST import * from slicc.ast.VarExprAST import * from slicc.ast.WakeUpAllDependentsStatementAST import * from slicc.ast.WakeUpDependentsStatementAST import * diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py index 823e08819..448954e63 100644 --- a/src/mem/slicc/parser.py +++ b/src/mem/slicc/parser.py @@ -156,6 +156,7 @@ class SLICC(Grammar): 'structure' : 'STRUCT', 'external_type' : 'EXTERN_TYPE', 'enumeration' : 'ENUM', + 'state_declaration' : 'STATE_DECL', 'peek' : 'PEEK', 'stall_and_wait' : 'STALL_AND_WAIT', 'wake_up_dependents' : 'WAKE_UP_DEPENDENTS', @@ -329,6 +330,12 @@ class SLICC(Grammar): p[4]["enumeration"] = "yes" p[0] = ast.EnumDeclAST(self, p[3], p[4], p[7]) + def p_decl__state_decl(self, p): + "decl : STATE_DECL '(' type pairs ')' '{' type_states '}'" + p[4]["enumeration"] = "yes" + p[4]["state_decl"] = "yes" + p[0] = ast.StateDeclAST(self, p[3], p[4], p[7]) + def p_decl__object(self, p): "decl : type ident pairs SEMI" p[0] = ast.ObjDeclAST(self, p[1], p[2], p[3]) @@ -387,6 +394,19 @@ class SLICC(Grammar): "type_enum : ident pairs SEMI" p[0] = ast.TypeFieldEnumAST(self, p[1], p[2]) + # States + def p_type_states__list(self, p): + "type_states : type_state type_states" + p[0] = [ p[1] ] + p[2] + + def p_type_states__empty(self, p): + "type_states : empty" + p[0] = [] + + def p_type_state(self, p): + "type_state : ident ',' enumeration pairs SEMI" + p[0] = ast.TypeFieldStateAST(self, p[1], p[3], p[4]) + # Type def p_types__multiple(self, p): "types : type ',' types" diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 1251196c9..3c5f860ea 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -347,6 +347,8 @@ static int m_num_controllers; // Set and Reset for cache_entry variable void set_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AbstractCacheEntry* m_new_cache_entry); void unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr); +// Set permissions for the cache_entry +void set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AccessPermission perm); ''') if self.TBEType != None: @@ -850,6 +852,15 @@ $c_ident::unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr) { m_cache_entry_ptr = 0; } + +void +$c_ident::set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, + AccessPermission perm) +{ + if (m_cache_entry_ptr != NULL) { + m_cache_entry_ptr->changePermission(perm); + } +} ''') if self.TBEType != None: @@ -1090,10 +1101,12 @@ ${ident}_Controller::doTransition(${ident}_Event event, ''') if self.TBEType != None and self.EntryType != None: code('${ident}_setState(m_tbe_ptr, m_cache_entry_ptr, addr, next_state);') + code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));') elif self.TBEType != None: code('${ident}_setState(m_tbe_ptr, addr, next_state);') elif self.EntryType != None: code('${ident}_setState(m_cache_entry_ptr, addr, next_state);') + code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));') else: code('${ident}_setState(addr, next_state);') diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index e521d544f..da9ecba3a 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -100,6 +100,9 @@ class Type(Symbol): self.isMachineType = (ident == "MachineType") + self.isStateDecl = ("state_decl" in self) + self.statePermPairs = [] + self.data_members = orderdict() # Methods @@ -158,6 +161,9 @@ class Type(Symbol): def methodIdAbstract(self, name, param_type_vec): return '_'.join([name] + [ pt.abstract_ident for pt in param_type_vec ]) + def statePermPairAdd(self, state_name, perm_name): + self.statePermPairs.append([state_name, perm_name]) + def methodAdd(self, name, return_type, param_type_vec): ident = self.methodId(name, param_type_vec) if ident in self.methods: @@ -446,6 +452,11 @@ ${{self.c_ident}}::print(ostream& out) const #include <string> #include "mem/ruby/common/Global.hh" +''') + if self.isStateDecl: + code('#include "mem/protocol/AccessPermission.hh"') + + code(''' // Class definition /** \\enum ${{self.c_ident}} @@ -491,6 +502,14 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj); for enum in self.enums.itervalues(): code('#define MACHINETYPE_${{enum.ident}} 1') + if self.isStateDecl: + code(''' + +// Code to convert the current state to an access permission +AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj); + +''') + # Trailer code(''' std::ostream& operator<<(std::ostream& out, const ${{self.c_ident}}& obj); @@ -519,6 +538,27 @@ using namespace std; ''') + if self.isStateDecl: + code(''' +// Code to convert the current state to an access permission +AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj) +{ + switch(obj) { +''') + # For each case + code.indent() + for statePerm in self.statePermPairs: + code(' case ${{self.c_ident}}_${{statePerm[0]}}:') + code(' return AccessPermission_${{statePerm[1]}};') + code.dedent() + code (''' + default: + panic("Unknown state access permission converstion for ${{self.c_ident}}"); + } +} + +''') + if self.isMachineType: for enum in self.enums.itervalues(): code('#include "mem/protocol/${{enum.ident}}_Controller.hh"') |