summaryrefslogtreecommitdiff
path: root/src/mem/slicc
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/slicc')
-rw-r--r--src/mem/slicc/ast/ActionDeclAST.py4
-rw-r--r--src/mem/slicc/ast/InPortDeclAST.py8
-rw-r--r--src/mem/slicc/ast/StallAndWaitStatementAST.py2
-rw-r--r--src/mem/slicc/symbols/StateMachine.py30
-rw-r--r--src/mem/slicc/symbols/Type.py5
5 files changed, 25 insertions, 24 deletions
diff --git a/src/mem/slicc/ast/ActionDeclAST.py b/src/mem/slicc/ast/ActionDeclAST.py
index 8015523ab..95a8b6322 100644
--- a/src/mem/slicc/ast/ActionDeclAST.py
+++ b/src/mem/slicc/ast/ActionDeclAST.py
@@ -48,10 +48,10 @@ class ActionDeclAST(DeclAST):
# Add new local vars
self.symtab.pushFrame()
- addr_type = self.symtab.find("Address", Type)
+ addr_type = self.symtab.find("Addr", Type)
if addr_type is None:
- self.error("Type 'Address' not declared.")
+ self.error("Type 'Addr' not declared.")
var = Var(self.symtab, "address", self.location, addr_type,
"addr", self.pairs)
diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
index da7357580..7a019a0e0 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -72,9 +72,9 @@ class InPortDeclAST(DeclAST):
param_types.append(type)
# Check for Address
- type = symtab.find("Address", Type)
+ type = symtab.find("Addr", Type)
if type is None:
- self.error("in_port decls require 'Address' type to be defined")
+ self.error("in_port decls require 'Addr' type to be defined")
param_types.append(type)
@@ -107,9 +107,9 @@ class InPortDeclAST(DeclAST):
param_types.append(type)
# Check for Address2
- type = symtab.find("Address", Type)
+ type = symtab.find("Addr", Type)
if type is None:
- self.error("in_port decls require 'Address' type to be defined")
+ self.error("in_port decls require 'Addr' type to be defined")
param_types.append(type)
diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py
index 08b0e340c..b2f622871 100644
--- a/src/mem/slicc/ast/StallAndWaitStatementAST.py
+++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py
@@ -39,7 +39,7 @@ class StallAndWaitStatementAST(StatementAST):
def generate(self, code, return_type):
self.in_port.assertType("InPort")
- self.address.assertType("Address")
+ self.address.assertType("Addr")
in_port_code = self.in_port.var.code
address_code = self.address.var.code
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 7a6d78458..03c78c8bf 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -349,7 +349,7 @@ TransitionResult doTransition(${ident}_Event event,
''')
code('''
- const Address addr);
+ Addr addr);
TransitionResult doTransitionWorker(${ident}_Event event,
${ident}_State state,
@@ -366,7 +366,7 @@ TransitionResult doTransitionWorker(${ident}_Event event,
''')
code('''
- const Address& addr);
+ Addr addr);
int m_counters[${ident}_State_NUM][${ident}_Event_NUM];
int m_event_counters[${ident}_Event_NUM];
@@ -410,21 +410,21 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
code('/** \\brief ${{action.desc}} */')
code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
'm_tbe_ptr, ${{self.EntryType.c_ident}}*& '
- 'm_cache_entry_ptr, const Address& addr);')
+ 'm_cache_entry_ptr, Addr addr);')
elif self.TBEType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
code('void ${{action.ident}}(${{self.TBEType.c_ident}}*& '
- 'm_tbe_ptr, const Address& addr);')
+ 'm_tbe_ptr, Addr addr);')
elif self.EntryType != None:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
code('void ${{action.ident}}(${{self.EntryType.c_ident}}*& '
- 'm_cache_entry_ptr, const Address& addr);')
+ 'm_cache_entry_ptr, Addr addr);')
else:
for action in self.actions.itervalues():
code('/** \\brief ${{action.desc}} */')
- code('void ${{action.ident}}(const Address& addr);')
+ code('void ${{action.ident}}(Addr addr);')
# the controller internal variables
code('''
@@ -930,7 +930,7 @@ $c_ident::recordCacheTrace(int cntrl, CacheRecorder* tr)
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr)
+$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.EntryType.c_ident}}*& m_cache_entry_ptr, Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
try {
@@ -951,7 +951,7 @@ $c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, ${{self.Entry
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, const Address& addr)
+$c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
${{action["c_code"]}}
@@ -966,7 +966,7 @@ $c_ident::${{action.ident}}(${{self.TBEType.c_ident}}*& m_tbe_ptr, const Address
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, const Address& addr)
+$c_ident::${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
${{action["c_code"]}}
@@ -981,7 +981,7 @@ $c_ident::${{action.ident}}(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, con
code('''
/** \\brief ${{action.desc}} */
void
-$c_ident::${{action.ident}}(const Address& addr)
+$c_ident::${{action.ident}}(Addr addr)
{
DPRINTF(RubyGenerated, "executing ${{action.ident}}\\n");
${{action["c_code"]}}
@@ -1181,7 +1181,7 @@ ${ident}_Controller::doTransition(${ident}_Event event,
${{self.TBEType.c_ident}}* m_tbe_ptr,
''')
code('''
- const Address addr)
+ Addr addr)
{
''')
code.indent()
@@ -1222,7 +1222,7 @@ if (result == TransitionResult_Valid) {
${ident}_State_to_string(next_state));
countTransition(state, event);
- DPRINTFR(ProtocolTrace, "%15d %3s %10s%20s %6s>%-6s %s %s\\n",
+ DPRINTFR(ProtocolTrace, "%15d %3s %10s%20s %6s>%-6s %#x %s\\n",
curTick(), m_version, "${ident}",
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
@@ -1246,7 +1246,7 @@ if (result == TransitionResult_Valid) {
code('''
} else if (result == TransitionResult_ResourceStall) {
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\\n",
curTick(), m_version, "${ident}",
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
@@ -1254,7 +1254,7 @@ if (result == TransitionResult_Valid) {
addr, "Resource Stall");
} else if (result == TransitionResult_ProtocolStall) {
DPRINTF(RubyGenerated, "stalling\\n");
- DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\\n",
+ DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\\n",
curTick(), m_version, "${ident}",
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
@@ -1283,7 +1283,7 @@ ${ident}_Controller::doTransitionWorker(${ident}_Event event,
${{self.EntryType.c_ident}}*& m_cache_entry_ptr,
''')
code('''
- const Address& addr)
+ Addr addr)
{
switch(HASH_FUN(state, event)) {
''')
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 73d6f9c69..5fd63d834 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -451,6 +451,7 @@ ${{self.c_ident}}::print(ostream& out) const
if self.isMachineType:
code('#include "base/misc.hh"')
code('#include "mem/ruby/common/Address.hh"')
+ code('#include "mem/ruby/common/TypeDefines.hh"')
code('struct MachineID;')
code('''
@@ -499,7 +500,7 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj);
for enum in self.enums.itervalues():
if enum.ident == "DMA":
code('''
-MachineID map_Address_to_DMA(const Address &addr);
+MachineID map_Address_to_DMA(const Addr &addr);
''')
code('''
@@ -750,7 +751,7 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj)
if enum.ident == "DMA":
code('''
MachineID
-map_Address_to_DMA(const Address &addr)
+map_Address_to_DMA(const Addr &addr)
{
MachineID dma = {MachineType_DMA, 0};
return dma;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 20:59:45 +0000