diff options
Diffstat (limited to 'src/mem')
35 files changed, 74 insertions, 77 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 26c9637f0..0ee0696d8 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -435,8 +435,8 @@ class Cache : public BaseCache /** serialize the state of the caches * We currently don't support checkpointing cache state, so this panics. */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; /** @@ -455,7 +455,7 @@ class CacheBlkVisitorWrapper : public CacheBlkVisitor CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) : cache(_cache), visitor(_visitor) {} - bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + bool operator()(CacheBlk &blk) override { return (cache.*visitor)(blk); } @@ -477,7 +477,7 @@ class CacheBlkIsDirtyVisitor : public CacheBlkVisitor CacheBlkIsDirtyVisitor() : _isDirty(false) {} - bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + bool operator()(CacheBlk &blk) override { if (blk.isDirty()) { _isDirty = true; return false; diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh index 308d371fe..eebfed827 100644 --- a/src/mem/cache/mshr_queue.hh +++ b/src/mem/cache/mshr_queue.hh @@ -255,7 +255,7 @@ class MSHRQueue : public Drainable return readyList.empty() ? MaxTick : readyList.front()->readyTime; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; }; #endif //__MEM_CACHE_MSHR_QUEUE_HH__ diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh index 2798c823f..af17252d8 100644 --- a/src/mem/cache/prefetch/stride.hh +++ b/src/mem/cache/prefetch/stride.hh @@ -48,7 +48,8 @@ #ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__ #define __MEM_CACHE_PREFETCH_STRIDE_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "mem/cache/prefetch/queued.hh" #include "params/StridePrefetcher.hh" @@ -99,7 +100,7 @@ class StridePrefetcher : public QueuedPrefetcher const int pcTableAssoc; const int pcTableSets; const std::string _name; - m5::hash_map<int, StrideEntry**> entries; + std::unordered_map<int, StrideEntry**> entries; StrideEntry** allocateNewContext(int context); }; diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index 9fe23ea91..e415603d9 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -407,7 +407,7 @@ public: * * \param visitor Visitor to call on each block. */ - void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE { + void forEachBlk(CacheBlkVisitor &visitor) override { for (unsigned i = 0; i < numSets * assoc; ++i) { if (!visitor(blks[i])) return; diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index def4c9b2c..1728ee48a 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -49,8 +49,8 @@ #define __MEM_CACHE_TAGS_FA_LRU_HH__ #include <list> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/cache/tags/base.hh" #include "mem/cache/blk.hh" #include "mem/packet.hh" @@ -109,7 +109,7 @@ class FALRU : public BaseTags FALRUBlk *tail; /** Hash table type mapping addresses to cache block pointers. */ - typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t; + typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; /** Iterator into the address hash table. */ typedef hash_t::const_iterator tagIterator; @@ -322,7 +322,7 @@ public: * * \param visitor Visitor to call on each block. */ - void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE { + void forEachBlk(CacheBlkVisitor &visitor) override { for (int i = 0; i < numBlocks; i++) { if (!visitor(blks[i])) return; diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh index d431a1d24..e99e9374f 100644 --- a/src/mem/coherent_xbar.hh +++ b/src/mem/coherent_xbar.hh @@ -258,7 +258,7 @@ class CoherentXBar : public BaseXBar * responses from so we can determine which snoop responses we * generated and which ones were merely forwarded. */ - m5::hash_set<RequestPtr> outstandingSnoop; + std::unordered_set<RequestPtr> outstandingSnoop; /** * Keep a pointer to the system to be allow to querying memory system diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh index fb8f5eeb7..df61b0b80 100644 --- a/src/mem/comm_monitor.hh +++ b/src/mem/comm_monitor.hh @@ -74,17 +74,17 @@ class CommMonitor : public MemObject */ CommMonitor(Params* params); - void init() M5_ATTR_OVERRIDE; - void regStats() M5_ATTR_OVERRIDE; - void startup() M5_ATTR_OVERRIDE; - void regProbePoints() M5_ATTR_OVERRIDE; + void init() override; + void regStats() override; + void startup() override; + void regProbePoints() override; public: // MemObject interfaces BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) M5_ATTR_OVERRIDE; + PortID idx = InvalidPortID) override; BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) M5_ATTR_OVERRIDE; + PortID idx = InvalidPortID) override; private: diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index bf0be04a7..a7f3e5602 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -872,14 +872,14 @@ class DRAMCtrl : public AbstractMemory DRAMCtrl(const DRAMCtrlParams* p); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); - virtual void init() M5_ATTR_OVERRIDE; - virtual void startup() M5_ATTR_OVERRIDE; - virtual void drainResume() M5_ATTR_OVERRIDE; + virtual void init() override; + virtual void startup() override; + virtual void drainResume() override; protected: diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh index 5d8e64282..77486de88 100644 --- a/src/mem/dramsim2.hh +++ b/src/mem/dramsim2.hh @@ -45,8 +45,8 @@ #define __MEM_DRAMSIM2_HH__ #include <queue> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/abstract_mem.hh" #include "mem/dramsim2_wrapper.hh" #include "mem/qport.hh" @@ -114,8 +114,8 @@ class DRAMSim2 : public AbstractMemory * done so that we can return the right packet on completion from * DRAMSim. */ - m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads; - m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites; + std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads; + std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites; /** * Count the number of outstanding transactions so that we can @@ -189,7 +189,7 @@ class DRAMSim2 : public AbstractMemory */ void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); diff --git a/src/mem/mem_checker.hh b/src/mem/mem_checker.hh index 0ec0f08df..6ceca74a7 100644 --- a/src/mem/mem_checker.hh +++ b/src/mem/mem_checker.hh @@ -44,9 +44,9 @@ #include <list> #include <map> #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "base/misc.hh" #include "base/types.hh" #include "debug/MemChecker.hh" @@ -184,7 +184,7 @@ class MemChecker : public SimObject * Map of Serial --> Transaction of all writes in cluster; contains * all, in-flight or already completed. */ - m5::hash_map<Serial, Transaction> writes; + std::unordered_map<Serial, Transaction> writes; private: Tick completeMax; @@ -509,7 +509,7 @@ class MemChecker : public SimObject * * Access via getByteTracker()! */ - m5::hash_map<Addr, ByteTracker> byte_trackers; + std::unordered_map<Addr, ByteTracker> byte_trackers; }; inline MemChecker::Serial diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh index f622bbbed..b9e020460 100644 --- a/src/mem/multi_level_page_table.hh +++ b/src/mem/multi_level_page_table.hh @@ -153,7 +153,7 @@ public: void unmap(Addr vaddr, int64_t size); bool isUnmapped(Addr vaddr, int64_t size); bool lookup(Addr vaddr, TheISA::TlbEntry &entry); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh index 4eabd1bc4..e9cf34bb0 100644 --- a/src/mem/packet_queue.hh +++ b/src/mem/packet_queue.hh @@ -188,7 +188,7 @@ class PacketQueue : public Drainable */ void retry(); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; }; class ReqPacketQueue : public PacketQueue diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index ddec104a7..7dcbbd65a 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -38,10 +38,10 @@ #define __MEM_PAGE_TABLE_HH__ #include <string> +#include <unordered_map> #include "arch/isa_traits.hh" #include "arch/tlb.hh" -#include "base/hashmap.hh" #include "base/types.hh" #include "config/the_isa.hh" #include "mem/request.hh" @@ -200,7 +200,7 @@ class PageTableBase : public Serializable class FuncPageTable : public PageTableBase { private: - typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable; + typedef std::unordered_map<Addr, TheISA::TlbEntry> PTable; typedef PTable::iterator PTableItr; PTable pTable; @@ -235,8 +235,8 @@ class FuncPageTable : public PageTableBase */ bool lookup(Addr vaddr, TheISA::TlbEntry &entry); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; /** diff --git a/src/mem/physical.hh b/src/mem/physical.hh index c577cd3ea..7f4c975f0 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -197,7 +197,7 @@ class PhysicalMemory : public Serializable * * @param os stream to serialize to */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; /** * Serialize a specific store. @@ -214,7 +214,7 @@ class PhysicalMemory : public Serializable * serialization, this action is independent of how the address * ranges are mapped to logical memories in the guest system. */ - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void unserialize(CheckpointIn &cp) override; /** * Unserialize a specific backing store, identified by a section. diff --git a/src/mem/probes/base.hh b/src/mem/probes/base.hh index ccb5ca749..78e6f6b8d 100644 --- a/src/mem/probes/base.hh +++ b/src/mem/probes/base.hh @@ -65,7 +65,7 @@ class BaseMemProbe : public SimObject public: BaseMemProbe(BaseMemProbeParams *params); - void regProbeListeners() M5_ATTR_OVERRIDE; + void regProbeListeners() override; protected: /** @@ -82,7 +82,7 @@ class BaseMemProbe : public SimObject : ProbeListenerArgBase(pm, name), parent(_parent) {} - void notify(const ProbePoints::PacketInfo &pkt_info) M5_ATTR_OVERRIDE { + void notify(const ProbePoints::PacketInfo &pkt_info) override { parent.handleRequest(pkt_info); } diff --git a/src/mem/probes/mem_trace.hh b/src/mem/probes/mem_trace.hh index 51f272812..d34235eef 100644 --- a/src/mem/probes/mem_trace.hh +++ b/src/mem/probes/mem_trace.hh @@ -52,8 +52,7 @@ class MemTraceProbe : public BaseMemProbe MemTraceProbe(MemTraceProbeParams *params); protected: - void handleRequest(const ProbePoints::PacketInfo &pkt_info) \ - M5_ATTR_OVERRIDE; + void handleRequest(const ProbePoints::PacketInfo &pkt_info) override; /** * Callback to flush and close all open output streams on exit. If diff --git a/src/mem/probes/stack_dist.hh b/src/mem/probes/stack_dist.hh index 8374672da..66b75109a 100644 --- a/src/mem/probes/stack_dist.hh +++ b/src/mem/probes/stack_dist.hh @@ -52,11 +52,10 @@ class StackDistProbe : public BaseMemProbe public: StackDistProbe(StackDistProbeParams *params); - void regStats() M5_ATTR_OVERRIDE; + void regStats() override; protected: - void handleRequest(const ProbePoints::PacketInfo &pkt_info) \ - M5_ATTR_OVERRIDE; + void handleRequest(const ProbePoints::PacketInfo &pkt_info) override; protected: // Cache line size to simulate diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index 90955447b..ded6f6f12 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -33,7 +33,6 @@ #include <iomanip> #include <iostream> -#include "base/hashmap.hh" #include "base/types.hh" const uint32_t ADDRESS_WIDTH = 64; // address width in bytes diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh index ebd44080b..9f12415c5 100644 --- a/src/mem/ruby/profiler/AddressProfiler.hh +++ b/src/mem/ruby/profiler/AddressProfiler.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_PROFILER_ADDRESSPROFILER_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/RubyRequest.hh" #include "mem/ruby/common/Address.hh" @@ -44,7 +44,7 @@ class Set; class AddressProfiler { public: - typedef m5::hash_map<Addr, AccessTraceForAddress> AddressMap; + typedef std::unordered_map<Addr, AccessTraceForAddress> AddressMap; public: AddressProfiler(int num_of_sequencers, Profiler *profiler); diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 146beadd6..7e45e8aeb 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -50,7 +50,6 @@ #include <vector> #include "base/callback.hh" -#include "base/hashmap.hh" #include "base/statistics.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/PrefetchBit.hh" diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 6e4022ea6..a8a3ba949 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -113,7 +113,7 @@ CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); + auto it = m_tag_index.find(tag); if (it != m_tag_index.end()) if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent) @@ -129,7 +129,7 @@ CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, { assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); + auto it = m_tag_index.find(tag); if (it != m_tag_index.end()) return it->second; return -1; // Not found diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 7ce674e61..72805b32b 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -31,9 +31,9 @@ #define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "base/statistics.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheResourceType.hh" @@ -168,7 +168,7 @@ class CacheMemory : public SimObject // The first index is the # of cache lines. // The second index is the the amount associativity. - m5::hash_map<Addr, int> m_tag_index; + std::unordered_map<Addr, int> m_tag_index; std::vector<std::vector<AbstractCacheEntry*> > m_cache; AbstractReplacementPolicy *m_replacementPolicy_ptr; diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh index 2b8b87628..61d5e1244 100644 --- a/src/mem/ruby/structures/PerfectCacheMemory.hh +++ b/src/mem/ruby/structures/PerfectCacheMemory.hh @@ -29,7 +29,8 @@ #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/common/Address.hh" @@ -87,7 +88,7 @@ class PerfectCacheMemory PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); // Data Members (m_prefix) - m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map; + std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map; }; template<class ENTRY> diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh index a4604fce8..e5296d1e8 100644 --- a/src/mem/ruby/structures/PersistentTable.hh +++ b/src/mem/ruby/structures/PersistentTable.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_STRUCTURES_PERSISTENTTABLE_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/MachineID.hh" @@ -77,7 +77,7 @@ class PersistentTable PersistentTable& operator=(const PersistentTable& obj); // Data Members (m_prefix) - typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap; + typedef std::unordered_map<Addr, PersistentTableEntry> AddressMap; AddressMap m_map; }; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index f5f31458b..75fe71dfb 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -60,7 +60,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; void wakeup(); void setDescription(const std::string& name) { m_description = name; }; diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh index 4a24a5b13..a39c5af2e 100644 --- a/src/mem/ruby/structures/TBETable.hh +++ b/src/mem/ruby/structures/TBETable.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_STRUCTURES_TBETABLE_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/ruby/common/Address.hh" template<class ENTRY> @@ -63,7 +63,7 @@ class TBETable TBETable& operator=(const TBETable& obj); // Data Members (m_prefix) - m5::hash_map<Addr, ENTRY> m_map; + std::unordered_map<Addr, ENTRY> m_map; private: int m_number_of_TBEs; diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh index 44110cf9f..822b370e8 100644 --- a/src/mem/ruby/system/CacheRecorder.hh +++ b/src/mem/ruby/system/CacheRecorder.hh @@ -37,7 +37,6 @@ #include <vector> -#include "base/hashmap.hh" #include "base/types.hh" #include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Address.hh" diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index f9d1b630e..1d5451f6e 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -108,7 +108,7 @@ class DMASequencer : public MemObject // A pointer to the controller is needed for atomic support. void setController(AbstractController* _cntrl) { m_controller = _cntrl; } uint32_t getId() { return m_version; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; /* SLICC callback */ void dataCallback(const DataBlock & dblk); diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index cbcc678d3..98fab8c4e 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -161,7 +161,7 @@ class RubyPort : public MemObject // void setController(AbstractController* _cntrl) { m_controller = _cntrl; } uint32_t getId() { return m_version; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; protected: void ruby_hit_callback(PacketPtr pkt); diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh index 7026f6756..23974e924 100644 --- a/src/mem/ruby/system/RubySystem.hh +++ b/src/mem/ruby/system/RubySystem.hh @@ -94,9 +94,9 @@ class RubySystem : public ClockedObject void resetStats(); void memWriteback(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; + void drainResume() override; void process(); void startup(); bool functionalRead(Packet *ptr); diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index aa4ac742a..26db6b6f8 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -634,10 +634,10 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) template <class KEY, class VALUE> std::ostream & -operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) +operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) { - typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); - typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); + auto i = map.begin(); + auto end = map.end(); out << "["; for (; i != end; ++i) diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 4716aa653..47af7ea1e 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/MachineType.hh" #include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/SequencerRequestType.hh" @@ -185,7 +185,7 @@ class Sequencer : public RubyPort Cycles m_data_cache_hit_latency; Cycles m_inst_cache_hit_latency; - typedef m5::hash_map<Addr, SequencerRequest*> RequestTable; + typedef std::unordered_map<Addr, SequencerRequest*> RequestTable; RequestTable m_writeRequestTable; RequestTable m_readRequestTable; // Global outstanding request count, across all request tables diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh index 98c41623f..c5b932bf0 100644 --- a/src/mem/simple_mem.hh +++ b/src/mem/simple_mem.hh @@ -185,7 +185,7 @@ class SimpleMemory : public AbstractMemory SimpleMemory(const SimpleMemoryParams *p); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh index 407b6f7f1..2a8d1ce21 100755 --- a/src/mem/snoop_filter.hh +++ b/src/mem/snoop_filter.hh @@ -45,9 +45,9 @@ #ifndef __MEM_SNOOP_FILTER_HH__ #define __MEM_SNOOP_FILTER_HH__ +#include <unordered_map> #include <utility> -#include "base/hashmap.hh" #include "mem/packet.hh" #include "mem/port.hh" #include "mem/qport.hh" @@ -218,7 +218,7 @@ class SnoopFilter : public SimObject { /** * HashMap of SnoopItems indexed by line address */ - typedef m5::hash_map<Addr, SnoopItem> SnoopFilterCache; + typedef std::unordered_map<Addr, SnoopItem> SnoopFilterCache; /** * Simple factory methods for standard return values. diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh index 79e9a5380..251ad62cb 100644 --- a/src/mem/xbar.hh +++ b/src/mem/xbar.hh @@ -52,9 +52,9 @@ #define __MEM_XBAR_HH__ #include <deque> +#include <unordered_map> #include "base/addr_range_map.hh" -#include "base/hashmap.hh" #include "base/types.hh" #include "mem/mem_object.hh" #include "mem/qport.hh" @@ -114,7 +114,7 @@ class BaseXBar : public MemObject * * @return 1 if busy or waiting to retry, or 0 if idle */ - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; /** * Get the crossbar layer's name @@ -327,7 +327,7 @@ class BaseXBar : public MemObject * the underlying Request pointer inside the Packet stays * constant. */ - m5::unordered_map<RequestPtr, PortID> routeTo; + std::unordered_map<RequestPtr, PortID> routeTo; /** all contigous ranges seen by this crossbar */ AddrRangeList xbarRanges; |