summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/bus.cc70
-rw-r--r--src/mem/bus.hh3
-rw-r--r--src/mem/physical.cc11
-rw-r--r--src/mem/physical.hh1
-rw-r--r--src/mem/request.hh41
5 files changed, 74 insertions, 52 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index e9a870b80..bd721dd68 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -260,19 +260,12 @@ Bus::findPort(Addr addr, int id)
{
/* An interval tree would be a better way to do this. --ali. */
int dest_id = -1;
- int i = 0;
- bool found = false;
AddrRangeIter iter;
+ range_map<Addr,int>::iterator i;
- while (i < portList.size() && !found)
- {
- if (portList[i].range == addr) {
- dest_id = portList[i].portId;
- found = true;
- DPRINTF(Bus, " found addr %#llx on device %d\n", addr, dest_id);
- }
- i++;
- }
+ i = portMap.find(RangeSize(addr,1));
+ if (i != portMap.end())
+ dest_id = i->second;
// Check if this matches the default range
if (dest_id == -1) {
@@ -463,13 +456,13 @@ Bus::recvStatusChange(Port::Status status, int id)
assert((id < interfaces.size() && id >= 0) || id == defaultId);
Port *port = interfaces[id];
- std::vector<DevMap>::iterator portIter;
+ range_map<Addr,int>::iterator portIter;
std::vector<DevMap>::iterator snoopIter;
// Clean out any previously existent ids
- for (portIter = portList.begin(); portIter != portList.end(); ) {
- if (portIter->portId == id)
- portIter = portList.erase(portIter);
+ for (portIter = portMap.begin(); portIter != portMap.end(); ) {
+ if (portIter->second == id)
+ portMap.erase(portIter++);
else
portIter++;
}
@@ -495,16 +488,14 @@ Bus::recvStatusChange(Port::Status status, int id)
}
for(iter = ranges.begin(); iter != ranges.end(); iter++) {
- DevMap dm;
- dm.portId = id;
- dm.range = *iter;
-
DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for id %d\n",
- dm.range.start, dm.range.end, id);
- portList.push_back(dm);
+ iter->start, iter->end, id);
+ if (portMap.insert(*iter, id) == portMap.end())
+ panic("Two devices with same range\n");
+
}
}
- DPRINTF(MMU, "port list has %d entries\n", portList.size());
+ DPRINTF(MMU, "port list has %d entries\n", portMap.size());
// tell all our peers that our address range has changed.
// Don't tell the device that caused this change, it already knows
@@ -519,7 +510,8 @@ Bus::recvStatusChange(Port::Status status, int id)
void
Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
{
- std::vector<DevMap>::iterator portIter;
+ std::vector<DevMap>::iterator snoopIter;
+ range_map<Addr,int>::iterator portIter;
AddrRangeIter dflt_iter;
bool subset;
@@ -534,37 +526,37 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
DPRINTF(BusAddrRanges, " -- Dflt: %#llx : %#llx\n",dflt_iter->start,
dflt_iter->end);
}
- for (portIter = portList.begin(); portIter != portList.end(); portIter++) {
+ for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) {
subset = false;
for (dflt_iter = defaultRange.begin(); dflt_iter != defaultRange.end();
dflt_iter++) {
- if ((portIter->range.start < dflt_iter->start &&
- portIter->range.end >= dflt_iter->start) ||
- (portIter->range.start < dflt_iter->end &&
- portIter->range.end >= dflt_iter->end))
+ if ((portIter->first.start < dflt_iter->start &&
+ portIter->first.end >= dflt_iter->start) ||
+ (portIter->first.start < dflt_iter->end &&
+ portIter->first.end >= dflt_iter->end))
fatal("Devices can not set ranges that itersect the default set\
but are not a subset of the default set.\n");
- if (portIter->range.start >= dflt_iter->start &&
- portIter->range.end <= dflt_iter->end) {
+ if (portIter->first.start >= dflt_iter->start &&
+ portIter->first.end <= dflt_iter->end) {
subset = true;
DPRINTF(BusAddrRanges, " -- %#llx : %#llx is a SUBSET\n",
- portIter->range.start, portIter->range.end);
+ portIter->first.start, portIter->first.end);
}
}
- if (portIter->portId != id && !subset) {
- resp.push_back(portIter->range);
+ if (portIter->second != id && !subset) {
+ resp.push_back(portIter->first);
DPRINTF(BusAddrRanges, " -- %#llx : %#llx\n",
- portIter->range.start, portIter->range.end);
+ portIter->first.start, portIter->first.end);
}
}
- for (portIter = portSnoopList.begin();
- portIter != portSnoopList.end(); portIter++)
+ for (snoopIter = portSnoopList.begin();
+ snoopIter != portSnoopList.end(); snoopIter++)
{
- if (portIter->portId != id) {
- snoop.push_back(portIter->range);
+ if (snoopIter->portId != id) {
+ snoop.push_back(snoopIter->range);
DPRINTF(BusAddrRanges, " -- Snoop: %#llx : %#llx\n",
- portIter->range.start, portIter->range.end);
+ snoopIter->range.start, snoopIter->range.end);
//@todo We need to properly insert snoop ranges
//not overlapping the ranges (multiple)
}
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index c472b6143..0ad4aad60 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -42,6 +42,7 @@
#include <inttypes.h>
#include "base/range.hh"
+#include "base/range_map.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
@@ -67,7 +68,7 @@ class Bus : public MemObject
int portId;
Range<Addr> range;
};
- std::vector<DevMap> portList;
+ range_map<Addr, int> portMap;
AddrRangeList defaultRange;
std::vector<DevMap> portSnoopList;
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 94f60ad80..6610e547d 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -65,6 +65,10 @@ PhysicalMemory::PhysicalMemory(Params *p)
fatal("Could not mmap!\n");
}
+ //If requested, initialize all the memory to 0
+ if(params()->zero)
+ memset(pmemAddr, 0, params()->addrRange.size());
+
pagePtr = 0;
}
@@ -191,7 +195,7 @@ PhysicalMemory::checkLockedAddrList(Request *req)
void
PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
{
- assert(pkt->getAddr() + pkt->getSize() > params()->addrRange.start &&
+ assert(pkt->getAddr() >= params()->addrRange.start &&
pkt->getAddr() + pkt->getSize() <= params()->addrRange.start +
params()->addrRange.size());
@@ -432,6 +436,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
Param<string> file;
Param<Range<Addr> > range;
Param<Tick> latency;
+ Param<bool> zero;
END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
@@ -439,7 +444,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
INIT_PARAM_DFLT(file, "memory mapped file", ""),
INIT_PARAM(range, "Device Address Range"),
- INIT_PARAM(latency, "Memory access latency")
+ INIT_PARAM(latency, "Memory access latency"),
+ INIT_PARAM(zero, "Zero initialize memory")
END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
@@ -449,6 +455,7 @@ CREATE_SIM_OBJECT(PhysicalMemory)
p->name = getInstanceName();
p->addrRange = range;
p->latency = latency;
+ p->zero = zero;
return new PhysicalMemory(p);
}
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 045e61612..af88bcaa0 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -154,6 +154,7 @@ class PhysicalMemory : public MemObject
std::string name;
Range<Addr> addrRange;
Tick latency;
+ bool zero;
};
protected:
diff --git a/src/mem/request.hh b/src/mem/request.hh
index e54984fcd..de0512e1c 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -49,26 +49,28 @@ class Request;
typedef Request* RequestPtr;
+/** ASI information for this request if it exsits. */
+const uint32_t ASI_BITS = 0x000FF;
/** The request is a Load locked/store conditional. */
-const unsigned LOCKED = 0x001;
+const uint32_t LOCKED = 0x00100;
/** The virtual address is also the physical address. */
-const unsigned PHYSICAL = 0x002;
+const uint32_t PHYSICAL = 0x00200;
/** The request is an ALPHA VPTE pal access (hw_ld). */
-const unsigned VPTE = 0x004;
+const uint32_t VPTE = 0x00400;
/** Use the alternate mode bits in ALPHA. */
-const unsigned ALTMODE = 0x008;
+const uint32_t ALTMODE = 0x00800;
/** The request is to an uncacheable address. */
-const unsigned UNCACHEABLE = 0x010;
+const uint32_t UNCACHEABLE = 0x01000;
/** The request should not cause a page fault. */
-const unsigned NO_FAULT = 0x020;
+const uint32_t NO_FAULT = 0x02000;
/** The request should be prefetched into the exclusive state. */
-const unsigned PF_EXCLUSIVE = 0x100;
+const uint32_t PF_EXCLUSIVE = 0x10000;
/** The request should be marked as LRU. */
-const unsigned EVICT_NEXT = 0x200;
+const uint32_t EVICT_NEXT = 0x20000;
/** The request should ignore unaligned access faults */
-const unsigned NO_ALIGN_FAULT = 0x400;
+const uint32_t NO_ALIGN_FAULT = 0x40000;
/** The request was an instruction read. */
-const unsigned INST_READ = 0x800;
+const uint32_t INST_READ = 0x80000;
class Request
{
@@ -95,6 +97,10 @@ class Request
/** The address space ID. */
int asid;
+
+ /** This request is to a memory mapped register. */
+ bool mmapedIpr;
+
/** The virtual address of the request. */
Addr vaddr;
@@ -164,6 +170,7 @@ class Request
validAsidVaddr = false;
validPC = false;
validScResult = false;
+ mmapedIpr = false;
}
/**
@@ -181,6 +188,7 @@ class Request
validAsidVaddr = true;
validPC = true;
validScResult = false;
+ mmapedIpr = false;
}
/** Set just the physical address. This should only be used to
@@ -215,6 +223,19 @@ class Request
/** Accessor function for asid.*/
int getAsid() { assert(validAsidVaddr); return asid; }
+ /** Accessor function for asi.*/
+ uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; }
+
+ /** Accessor function for asi.*/
+ void setAsi(uint8_t a)
+ { assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; }
+
+ /** Accessor function for asi.*/
+ bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; }
+
+ /** Accessor function for asi.*/
+ void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; }
+
/** Accessor function to check if sc result is valid. */
bool scResultValid() { return validScResult; }
/** Accessor function for store conditional return value.*/
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-04 03:08:46 +0000