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-rw-r--r--src/mem/cache/cache.cc6
-rw-r--r--src/mem/dram_ctrl.cc2
-rw-r--r--src/mem/qport.hh4
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index aa95d5604..a03790abc 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -666,7 +666,7 @@ Cache::recvTimingReq(PacketPtr pkt)
// lat, neglecting responseLatency, modelling hit latency
// just as lookupLatency or or the value of lat overriden
// by access(), that calls accessBlock() function.
- cpuSidePort->schedTimingResp(pkt, request_time);
+ cpuSidePort->schedTimingResp(pkt, request_time, true);
} else {
// queue the packet for deletion, as the sending cache is
// still relying on it; if the block is found in access(),
@@ -723,7 +723,7 @@ Cache::recvTimingReq(PacketPtr pkt)
std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize());
// request_time is used here, taking into account lat and the delay
// charged if the packet comes from the xbar.
- cpuSidePort->schedTimingResp(pkt, request_time);
+ cpuSidePort->schedTimingResp(pkt, request_time, true);
// If an outstanding request is in progress (we found an
// MSHR) this is set to null
@@ -1330,7 +1330,7 @@ Cache::recvTimingResp(PacketPtr pkt)
}
// Reset the bus additional time as it is now accounted for
tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
- cpuSidePort->schedTimingResp(tgt_pkt, completion_time);
+ cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
break;
case MSHR::Target::FromPrefetcher:
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index abf570910..2364834e3 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -860,7 +860,7 @@ DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
// queue the packet in the response queue to be sent out after
// the static latency has passed
- port.schedTimingResp(pkt, response_time);
+ port.schedTimingResp(pkt, response_time, true);
} else {
// @todo the packet is going to be deleted, and the DRAMPacket
// is still having a pointer to it
diff --git a/src/mem/qport.hh b/src/mem/qport.hh
index 94bcc53fd..b15bdfec2 100644
--- a/src/mem/qport.hh
+++ b/src/mem/qport.hh
@@ -88,8 +88,8 @@ class QueuedSlavePort : public SlavePort
* @param pkt Packet to send
* @param when Absolute time (in ticks) to send packet
*/
- void schedTimingResp(PacketPtr pkt, Tick when)
- { respQueue.schedSendTiming(pkt, when); }
+ void schedTimingResp(PacketPtr pkt, Tick when, bool force_order = false)
+ { respQueue.schedSendTiming(pkt, when, force_order); }
/** Check the list of buffered packets against the supplied
* functional request. */