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-rw-r--r--src/mem/ruby/network/Network.py73
-rw-r--r--src/mem/ruby/network/topologies/Crossbar.py40
-rw-r--r--src/mem/ruby/network/topologies/Mesh.py103
-rw-r--r--src/mem/ruby/network/topologies/MeshDirCorners.py122
-rw-r--r--src/mem/ruby/network/topologies/SConscript37
5 files changed, 302 insertions, 73 deletions
diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py
index aabf023a3..1fdf15634 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -56,79 +56,6 @@ class Topology(SimObject):
print_config = Param.Bool(False,
"display topology config in the stats file")
-def makeCrossbar(nodes):
- ext_links = [ExtLink(ext_node=n, int_node=i)
- for (i, n) in enumerate(nodes)]
- xbar = len(nodes) # node ID for crossbar switch
- int_links = [IntLink(node_a=i, node_b=xbar) for i in range(len(nodes))]
- return Topology(ext_links=ext_links, int_links=int_links,
- num_int_nodes=len(nodes)+1)
-
-def makeMesh(nodes, num_routers, num_rows):
- #
- # There must be an evenly divisible number of cntrls to routers
- # Also, obviously the number or rows must be <= the number of routers
- #
- cntrls_per_router, remainder = divmod(len(nodes), num_routers)
- assert(num_rows <= num_routers)
- num_columns = int(num_routers / num_rows)
- assert(num_columns * num_rows == num_routers)
-
- #
- # Add all but the remainder nodes to the list of nodes to be uniformly
- # distributed across the network.
- #
- network_nodes = []
- remainder_nodes = []
- for node_index in xrange(len(nodes)):
- if node_index < (len(nodes) - remainder):
- network_nodes.append(nodes[node_index])
- else:
- remainder_nodes.append(nodes[node_index])
-
- #
- # Connect each node to the appropriate router
- #
- ext_links = []
- for (i, n) in enumerate(network_nodes):
- cntrl_level, router_id = divmod(i, num_routers)
- assert(cntrl_level < cntrls_per_router)
- ext_links.append(ExtLink(ext_node=n, int_node=router_id))
-
- #
- # Connect the remainding nodes to router 0. These should only be DMA nodes.
- #
- for (i, node) in enumerate(remainder_nodes):
- assert(node.type == 'DMA_Controller')
- assert(i < remainder)
- ext_links.append(ExtLink(ext_node=node, int_node=0))
-
- #
- # Create the mesh links. First row (east-west) links then column
- # (north-south) links
- #
- int_links = []
- for row in xrange(num_rows):
- for col in xrange(num_columns):
- if (col + 1 < num_columns):
- east_id = col + (row * num_columns)
- west_id = (col + 1) + (row * num_columns)
- int_links.append(IntLink(node_a=east_id,
- node_b=west_id,
- weight=1))
- for col in xrange(num_columns):
- for row in xrange(num_rows):
- if (row + 1 < num_rows):
- north_id = col + (row * num_columns)
- south_id = col + ((row + 1) * num_columns)
- int_links.append(IntLink(node_a=north_id,
- node_b=south_id,
- weight=2))
-
- return Topology(ext_links=ext_links,
- int_links=int_links,
- num_int_nodes=num_routers)
-
class RubyNetwork(SimObject):
type = 'RubyNetwork'
cxx_class = 'Network'
diff --git a/src/mem/ruby/network/topologies/Crossbar.py b/src/mem/ruby/network/topologies/Crossbar.py
new file mode 100644
index 000000000..18c8be251
--- /dev/null
+++ b/src/mem/ruby/network/topologies/Crossbar.py
@@ -0,0 +1,40 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+from m5.params import *
+from m5.objects import *
+
+def makeTopology(nodes, options):
+ ext_links = [ExtLink(ext_node=n, int_node=i)
+ for (i, n) in enumerate(nodes)]
+ xbar = len(nodes) # node ID for crossbar switch
+ int_links = [IntLink(node_a=i, node_b=xbar) for i in range(len(nodes))]
+ return Topology(ext_links=ext_links, int_links=int_links,
+ num_int_nodes=len(nodes)+1)
+
+
diff --git a/src/mem/ruby/network/topologies/Mesh.py b/src/mem/ruby/network/topologies/Mesh.py
new file mode 100644
index 000000000..6871bec1f
--- /dev/null
+++ b/src/mem/ruby/network/topologies/Mesh.py
@@ -0,0 +1,103 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+from m5.params import *
+from m5.objects import *
+
+#
+# Makes a generic mesh assuming an equal number of cache and directory cntrls
+#
+
+def makeTopology(nodes, options):
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ #
+ # There must be an evenly divisible number of cntrls to routers
+ # Also, obviously the number or rows must be <= the number of routers
+ #
+ cntrls_per_router, remainder = divmod(len(nodes), num_routers)
+ assert(num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+
+ #
+ # Add all but the remainder nodes to the list of nodes to be uniformly
+ # distributed across the network.
+ #
+ network_nodes = []
+ remainder_nodes = []
+ for node_index in xrange(len(nodes)):
+ if node_index < (len(nodes) - remainder):
+ network_nodes.append(nodes[node_index])
+ else:
+ remainder_nodes.append(nodes[node_index])
+
+ #
+ # Connect each node to the appropriate router
+ #
+ ext_links = []
+ for (i, n) in enumerate(network_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < cntrls_per_router)
+ ext_links.append(ExtLink(ext_node=n, int_node=router_id))
+
+ #
+ # Connect the remainding nodes to router 0. These should only be DMA nodes.
+ #
+ for (i, node) in enumerate(remainder_nodes):
+ assert(node.type == 'DMA_Controller')
+ assert(i < remainder)
+ ext_links.append(ExtLink(ext_node=node, int_node=0))
+
+ #
+ # Create the mesh links. First row (east-west) links then column
+ # (north-south) links
+ #
+ int_links = []
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ east_id = col + (row * num_columns)
+ west_id = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(node_a=east_id,
+ node_b=west_id,
+ weight=1))
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ north_id = col + (row * num_columns)
+ south_id = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(node_a=north_id,
+ node_b=south_id,
+ weight=2))
+
+ return Topology(ext_links=ext_links,
+ int_links=int_links,
+ num_int_nodes=num_routers)
diff --git a/src/mem/ruby/network/topologies/MeshDirCorners.py b/src/mem/ruby/network/topologies/MeshDirCorners.py
new file mode 100644
index 000000000..8b08241ae
--- /dev/null
+++ b/src/mem/ruby/network/topologies/MeshDirCorners.py
@@ -0,0 +1,122 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+from m5.params import *
+from m5.objects import *
+
+#
+# This file contains a special network creation function. This networks is not
+# general and will only work with specific system configurations. The network
+# specified is similar to GEMS old file specified network.
+#
+
+def makeTopology(nodes, options):
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ #
+ # First determine which nodes are cache cntrls vs. dirs vs. dma
+ #
+ cache_nodes = []
+ dir_nodes = []
+ dma_nodes = []
+ for node in nodes:
+ if node.type == 'L1Cache_Controller' or \
+ node.type == 'L2Cache_Controller':
+ cache_nodes.append(node)
+ elif node.type == 'Directory_Controller':
+ dir_nodes.append(node)
+ elif node.type == 'DMA_Controller':
+ dma_nodes.append(node)
+
+ #
+ # Obviously the number or rows must be <= the number of routers and evenly
+ # divisible. Also the number of caches must be a multiple of the number of
+ # routers and the number of directories must be four.
+ #
+ assert(num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+ caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
+ assert(remainder == 0)
+ assert(len(dir_nodes) == 4)
+
+ #
+ # Connect each cache controller to the appropriate router
+ #
+ ext_links = []
+ for (i, n) in enumerate(cache_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < caches_per_router)
+ ext_links.append(ExtLink(ext_node=n, int_node=router_id))
+
+ #
+ # Connect the dir nodes to the corners.
+ #
+ ext_links.append(ExtLink(ext_node=dir_nodes[0], int_node=0))
+ ext_links.append(ExtLink(ext_node=dir_nodes[1], int_node=(num_columns - 1)))
+
+ ext_links.append(ExtLink(ext_node=dir_nodes[2],
+ int_node=(num_routers - num_columns)))
+
+ ext_links.append(ExtLink(ext_node=dir_nodes[3], int_node=(num_routers - 1)))
+
+ #
+ # Connect the dma nodes to router 0. These should only be DMA nodes.
+ #
+ for (i, node) in enumerate(dma_nodes):
+ assert(node.type == 'DMA_Controller')
+ ext_links.append(ExtLink(ext_node=node, int_node=0))
+
+ #
+ # Create the mesh links. First row (east-west) links then column
+ # (north-south) links
+ #
+ int_links = []
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ east_id = col + (row * num_columns)
+ west_id = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(node_a=east_id,
+ node_b=west_id,
+ weight=1))
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ north_id = col + (row * num_columns)
+ south_id = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(node_a=north_id,
+ node_b=south_id,
+ weight=2))
+
+ return Topology(ext_links=ext_links,
+ int_links=int_links,
+ num_int_nodes=num_routers)
+
diff --git a/src/mem/ruby/network/topologies/SConscript b/src/mem/ruby/network/topologies/SConscript
new file mode 100644
index 000000000..71ee7809c
--- /dev/null
+++ b/src/mem/ruby/network/topologies/SConscript
@@ -0,0 +1,37 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+Import('*')
+
+if not env['RUBY']:
+ Return()
+
+PySource('', 'Crossbar.py')
+PySource('', 'Mesh.py')
+PySource('', 'MeshDirCorners.py')
+