5 files changed, 0 insertions, 99 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 89293430f..1536ada6e 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2328,38 +2328,6 @@ BaseCache::regStats()
         overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
     }
 
-#if 0
-    // MSHR access formulas
-    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
-        MemCmd cmd(access_idx);
-        const string &cstr = cmd.toString();
-
-        mshrAccesses[access_idx]
-            .name(name() + "." + cstr + "_mshr_accesses")
-            .desc("number of " + cstr + " mshr accesses(hits+misses)")
-            .flags(total | nozero | nonan)
-            ;
-        mshrAccesses[access_idx] =
-            mshr_hits[access_idx] + mshr_misses[access_idx]
-            + mshr_uncacheable[access_idx];
-    }
-
-    demandMshrAccesses
-        .name(name() + ".demand_mshr_accesses")
-        .desc("number of demand (read+write) mshr accesses")
-        .flags(total | nozero | nonan)
-        ;
-    demandMshrAccesses = demandMshrHits + demandMshrMisses;
-
-    overallMshrAccesses
-        .name(name() + ".overall_mshr_accesses")
-        .desc("number of overall (read+write) mshr accesses")
-        .flags(total | nozero | nonan)
-        ;
-    overallMshrAccesses = overallMshrHits + overallMshrMisses
-        + overallMshrUncacheable;
-#endif
-
     // MSHR miss rate formulas
     for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
         MemCmd cmd(access_idx);
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index bf190a591..c4e39716f 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1007,15 +1007,6 @@ class BaseCache : public ClockedObject
     /** Total cycle latency of overall MSHR misses. */
     Stats::Formula overallMshrUncacheableLatency;
 
-#if 0
-    /** The total number of MSHR accesses per command and thread. */
-    Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
-    /** The total number of demand MSHR accesses. */
-    Stats::Formula demandMshrAccesses;
-    /** The total number of MSHR accesses. */
-    Stats::Formula overallMshrAccesses;
-#endif
-
     /** The miss rate in the MSHRs pre command and thread. */
     Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
     /** The demand miss rate in the MSHRs. */
diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc
index 5f8725249..61ee2ae28 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -984,9 +984,6 @@ GPUCoalescer::print(ostream& out) const
 void
 GPUCoalescer::checkCoherence(Addr addr)
 {
-#ifdef CHECK_COHERENCE
-    m_ruby_system->checkGlobalCoherenceInvariant(addr);
-#endif
 }
 
 void
diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc
index 3d0470ca3..572f5fe07 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -508,58 +508,6 @@ RubySystem::functionalWrite(PacketPtr pkt)
     return true;
 }
 
-#ifdef CHECK_COHERENCE
-// This code will check for cases if the given cache block is exclusive in
-// one node and shared in another-- a coherence violation
-//
-// To use, the SLICC specification must call sequencer.checkCoherence(address)
-// when the controller changes to a state with new permissions.  Do this
-// in setState.  The SLICC spec must also define methods "isBlockShared"
-// and "isBlockExclusive" that are specific to that protocol
-//
-void
-RubySystem::checkGlobalCoherenceInvariant(const Address& addr)
-{
-#if 0
-    NodeID exclusive = -1;
-    bool sharedDetected = false;
-    NodeID lastShared = -1;
-
-    for (int i = 0; i < m_chip_vector.size(); i++) {
-        if (m_chip_vector[i]->isBlockExclusive(addr)) {
-            if (exclusive != -1) {
-                // coherence violation
-                WARN_EXPR(exclusive);
-                WARN_EXPR(m_chip_vector[i]->getID());
-                WARN_EXPR(addr);
-                WARN_EXPR(getTime());
-                ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips");
-            } else if (sharedDetected) {
-                WARN_EXPR(lastShared);
-                WARN_EXPR(m_chip_vector[i]->getID());
-                WARN_EXPR(addr);
-                WARN_EXPR(getTime());
-                ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
-            } else {
-                exclusive = m_chip_vector[i]->getID();
-            }
-        } else if (m_chip_vector[i]->isBlockShared(addr)) {
-            sharedDetected = true;
-            lastShared = m_chip_vector[i]->getID();
-
-            if (exclusive != -1) {
-                WARN_EXPR(lastShared);
-                WARN_EXPR(exclusive);
-                WARN_EXPR(addr);
-                WARN_EXPR(getTime());
-                ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
-            }
-        }
-    }
-#endif
-}
-#endif
-
 RubySystem *
 RubySystemParams::create()
 {
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index a282995da..ba67311c7 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -685,9 +685,6 @@ Sequencer::print(ostream& out) const
 void
 Sequencer::checkCoherence(Addr addr)
 {
-#ifdef CHECK_COHERENCE
-    m_ruby_system->checkGlobalCoherenceInvariant(addr);
-#endif
 }
 
 void