diff options
Diffstat (limited to 'src/mem')
37 files changed, 197 insertions, 267 deletions
diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc index 546dd6906..958a8ad4c 100644 --- a/src/mem/addr_mapper.cc +++ b/src/mem/addr_mapper.cc @@ -53,23 +53,15 @@ AddrMapper::init() fatal("Address mapper is not connected on both sides.\n"); } -BaseMasterPort& -AddrMapper::getMasterPort(const std::string& if_name, PortID idx) +Port & +AddrMapper::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -AddrMapper::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave") { + } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh index 6765638e9..6b47cfcb8 100644 --- a/src/mem/addr_mapper.hh +++ b/src/mem/addr_mapper.hh @@ -62,11 +62,8 @@ class AddrMapper : public MemObject virtual ~AddrMapper() { } - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init(); diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index 1066f47a0..7428e7f77 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -85,24 +85,16 @@ Bridge::Bridge(Params *p) { } -BaseMasterPort& -Bridge::getMasterPort(const std::string &if_name, PortID idx) +Port & +Bridge::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") return masterPort; - else - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); -} - -BaseSlavePort& -Bridge::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "slave") + else if (if_name == "slave") return slavePort; else // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index bb7727717..906640355 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -316,10 +316,8 @@ class Bridge : public MemObject public: - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init(); diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 50622d776..19655a57e 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -185,23 +185,15 @@ BaseCache::init() forwardSnoops = cpuSidePort.isSnooping(); } -BaseMasterPort & -BaseCache::getMasterPort(const std::string &if_name, PortID idx) +Port & +BaseCache::getPort(const std::string &if_name, PortID idx) { if (if_name == "mem_side") { return memSidePort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort & -BaseCache::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "cpu_side") { + } else if (if_name == "cpu_side") { return cpuSidePort; - } else { - return MemObject::getSlavePort(if_name, idx); + } else { + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index a7b25ff2f..a45dcba6f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -1028,10 +1028,8 @@ class BaseCache : public MemObject void init() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * Query block size of a cache. diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc index 223d1cc9f..f27027dfd 100644 --- a/src/mem/comm_monitor.cc +++ b/src/mem/comm_monitor.cc @@ -83,23 +83,15 @@ CommMonitor::regProbePoints() ppPktResp.reset(new ProbePoints::Packet(getProbeManager(), "PktResponse")); } -BaseMasterPort& -CommMonitor::getMasterPort(const std::string& if_name, PortID idx) +Port & +CommMonitor::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -CommMonitor::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave") { + } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh index dac71185c..1eea6a535 100644 --- a/src/mem/comm_monitor.hh +++ b/src/mem/comm_monitor.hh @@ -84,11 +84,8 @@ class CommMonitor : public MemObject void regProbePoints() override; public: // MemObject interfaces - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) override; - - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; private: diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index b6ec4653d..dd03cf113 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -2845,11 +2845,11 @@ DRAMCtrl::recvFunctional(PacketPtr pkt) functionalAccess(pkt); } -BaseSlavePort& -DRAMCtrl::getSlavePort(const string &if_name, PortID idx) +Port & +DRAMCtrl::getPort(const string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index a5f2fbe3e..d09223b4b 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -1176,8 +1176,8 @@ class DRAMCtrl : public QoS::MemCtrl DrainState drain() override; - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init() override; virtual void startup() override; diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc index 6fe854364..f0c612120 100644 --- a/src/mem/dramsim2.cc +++ b/src/mem/dramsim2.cc @@ -336,11 +336,11 @@ void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle) signalDrainDone(); } -BaseSlavePort& -DRAMSim2::getSlavePort(const std::string &if_name, PortID idx) +Port & +DRAMSim2::getPort(const std::string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh index 6444f75d6..2fd140bb4 100644 --- a/src/mem/dramsim2.hh +++ b/src/mem/dramsim2.hh @@ -191,8 +191,8 @@ class DRAMSim2 : public AbstractMemory DrainState drain() override; - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void init() override; void startup() override; diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc index 373aa84fe..799f85036 100644 --- a/src/mem/external_master.cc +++ b/src/mem/external_master.cc @@ -60,9 +60,8 @@ ExternalMaster::ExternalMaster(ExternalMasterParams *params) : masterId(params->system->getMasterId(this)) {} -BaseMasterPort & -ExternalMaster::getMasterPort(const std::string &if_name, - PortID idx) +Port & +ExternalMaster::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") { DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n", @@ -84,7 +83,7 @@ ExternalMaster::getMasterPort(const std::string &if_name, } return *externalPort; } else { - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh index d27cb4df1..42ac67c03 100644 --- a/src/mem/external_master.hh +++ b/src/mem/external_master.hh @@ -67,18 +67,18 @@ class ExternalMaster : public MemObject { public: /** Derive from this class to create an external port interface */ - class Port : public MasterPort + class ExternalPort : public MasterPort { protected: ExternalMaster &owner; public: - Port(const std::string &name_, + ExternalPort(const std::string &name_, ExternalMaster &owner_) : MasterPort(name_, &owner_), owner(owner_) { } - ~Port() { } + ~ExternalPort() { } /** Any or all of recv... can be overloaded to provide the port's * functionality */ @@ -93,14 +93,14 @@ class ExternalMaster : public MemObject public: /** Create or find an external port which can be bound. Returns * NULL on failure */ - virtual Port *getExternalPort( + virtual ExternalPort *getExternalPort( const std::string &name, ExternalMaster &owner, const std::string &port_data) = 0; }; protected: /** The peer port for the gem5 port "port" */ - Port *externalPort; + ExternalPort *externalPort; /** Name of the bound port. This will be name() + ".port" */ std::string portName; @@ -120,9 +120,9 @@ class ExternalMaster : public MemObject public: ExternalMaster(ExternalMasterParams *params); - /** MasterPort interface. Responds only to port "port" */ - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + /** Port interface. Responds only to port "port" */ + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** Register a handler which can provide ports with port_type == * handler_name */ diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc index ac93e669c..6266f6649 100644 --- a/src/mem/external_slave.cc +++ b/src/mem/external_slave.cc @@ -49,7 +49,7 @@ * a message. The stub port can be used to configure and test a system * where the external port is used for a peripheral before connecting * the external port */ -class StubSlavePort : public ExternalSlave::Port +class StubSlavePort : public ExternalSlave::ExternalPort { public: void processResponseEvent(); @@ -66,7 +66,7 @@ class StubSlavePort : public ExternalSlave::Port StubSlavePort(const std::string &name_, ExternalSlave &owner_) : - ExternalSlave::Port(name_, owner_), + ExternalSlave::ExternalPort(name_, owner_), responseEvent([this]{ processResponseEvent(); }, name()), responsePacket(NULL), mustRetry(false) { } @@ -83,7 +83,7 @@ class StubSlavePortHandler : public ExternalSlave::Handler { public: - ExternalSlave::Port *getExternalPort( + ExternalSlave::ExternalPort *getExternalPort( const std::string &name_, ExternalSlave &owner, const std::string &port_data) @@ -175,7 +175,7 @@ std::map<std::string, ExternalSlave::Handler *> ExternalSlave::portHandlers; AddrRangeList -ExternalSlave::Port::getAddrRanges() const +ExternalSlave::ExternalPort::getAddrRanges() const { return owner.addrRanges; } @@ -193,9 +193,8 @@ ExternalSlave::ExternalSlave(ExternalSlaveParams *params) : registerHandler("stub", new StubSlavePortHandler); } -BaseSlavePort & -ExternalSlave::getSlavePort(const std::string &if_name, - PortID idx) +Port & +ExternalSlave::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") { DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n", @@ -217,7 +216,7 @@ ExternalSlave::getSlavePort(const std::string &if_name, } return *externalPort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh index 2bb0be869..7290d6339 100644 --- a/src/mem/external_slave.hh +++ b/src/mem/external_slave.hh @@ -67,18 +67,18 @@ class ExternalSlave : public MemObject { public: /** Derive from this class to create an external port interface */ - class Port : public SlavePort + class ExternalPort : public SlavePort { protected: ExternalSlave &owner; public: - Port(const std::string &name_, + ExternalPort(const std::string &name_, ExternalSlave &owner_) : SlavePort(name_, &owner_), owner(owner_) { } - ~Port() { } + ~ExternalPort() { } /** Any or all of recv... can be overloaded to provide the port's * functionality */ @@ -95,14 +95,14 @@ class ExternalSlave : public MemObject public: /** Create or find an external port which can be bound. Returns * NULL on failure */ - virtual Port *getExternalPort( + virtual ExternalPort *getExternalPort( const std::string &name, ExternalSlave &owner, const std::string &port_data) = 0; }; protected: /** The peer port for the gem5 port "port" */ - Port *externalPort; + ExternalPort *externalPort; /** Name of the bound port. This will be name() + ".port" */ std::string portName; @@ -126,9 +126,9 @@ class ExternalSlave : public MemObject public: ExternalSlave(ExternalSlaveParams *params); - /** SlavePort interface. Responds only to port "port" */ - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + /** Port interface. Responds only to port "port" */ + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** Register a handler which can provide ports with port_type == * handler_name */ diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc index 75c797c32..8364b9198 100644 --- a/src/mem/mem_checker_monitor.cc +++ b/src/mem/mem_checker_monitor.cc @@ -73,23 +73,15 @@ MemCheckerMonitor::init() fatal("Communication monitor is not connected on both sides.\n"); } -BaseMasterPort& -MemCheckerMonitor::getMasterPort(const std::string& if_name, PortID idx) +Port & +MemCheckerMonitor::getPort(const std::string &if_name, PortID idx) { if (if_name == "master" || if_name == "mem_side") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -MemCheckerMonitor::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave" || if_name == "cpu_side") { + } else if (if_name == "slave" || if_name == "cpu_side") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh index e3a8832b5..0564a8178 100644 --- a/src/mem/mem_checker_monitor.hh +++ b/src/mem/mem_checker_monitor.hh @@ -70,11 +70,8 @@ class MemCheckerMonitor : public MemObject /** Destructor */ ~MemCheckerMonitor(); - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void init(); diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc index b3c89d2a3..67a9664f8 100644 --- a/src/mem/mem_delay.cc +++ b/src/mem/mem_delay.cc @@ -60,23 +60,15 @@ MemDelay::init() } -BaseMasterPort& -MemDelay::getMasterPort(const std::string& if_name, PortID idx) +Port & +MemDelay::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") { return masterPort; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -MemDelay::getSlavePort(const std::string& if_name, PortID idx) -{ - if (if_name == "slave") { + } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/mem_delay.hh b/src/mem/mem_delay.hh index 7ecb656f5..789d965c8 100644 --- a/src/mem/mem_delay.hh +++ b/src/mem/mem_delay.hh @@ -69,12 +69,9 @@ class MemDelay : public MemObject void init() override; - protected: // Port interfaces - BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - - BaseSlavePort& getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + protected: // Port interface + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; class MasterPort : public QueuedMasterPort { diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc index 766eceeb7..c88905d09 100644 --- a/src/mem/mem_object.cc +++ b/src/mem/mem_object.cc @@ -47,15 +47,3 @@ MemObject::MemObject(const Params *params) : ClockedObject(params) { } - -BaseMasterPort& -MemObject::getMasterPort(const std::string& if_name, PortID idx) -{ - fatal("%s does not have any master port named %s\n", name(), if_name); -} - -BaseSlavePort& -MemObject::getSlavePort(const std::string& if_name, PortID idx) -{ - fatal("%s does not have any slave port named %s\n", name(), if_name); -} diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh index e12b30661..3ae9c4adf 100644 --- a/src/mem/mem_object.hh +++ b/src/mem/mem_object.hh @@ -54,8 +54,7 @@ #include "sim/clocked_object.hh" /** - * The MemObject class extends the ClockedObject with accessor functions - * to get its master and slave ports. + * The MemObject class extends the ClockedObject for historical reasons. */ class MemObject : public ClockedObject { @@ -65,32 +64,6 @@ class MemObject : public ClockedObject { return dynamic_cast<const Params *>(_params); } MemObject(const Params *params); - - /** - * Get a master port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - - /** - * Get a slave port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); }; #endif //__MEM_MEM_OBJECT_HH__ diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc index 77cfbaf22..3ff2339d5 100644 --- a/src/mem/qos/mem_sink.cc +++ b/src/mem/qos/mem_sink.cc @@ -106,11 +106,11 @@ MemSinkCtrl::recvFunctional(PacketPtr pkt) pkt->popLabel(); } -BaseSlavePort & -MemSinkCtrl::getSlavePort(const std::string &interface, PortID idx) +Port & +MemSinkCtrl::getPort(const std::string &interface, PortID idx) { if (interface != "port") { - return MemObject::getSlavePort(interface, idx); + return MemObject::getPort(interface, idx); } else { return port; } diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh index 84258e0ac..9a51269dc 100644 --- a/src/mem/qos/mem_sink.hh +++ b/src/mem/qos/mem_sink.hh @@ -133,12 +133,11 @@ class MemSinkCtrl : public MemCtrl /** * Getter method to access this memory's slave port * - * @param interface interface name + * @param if_name interface name * @param idx port ID number * @return reference to this memory's slave port */ - BaseSlavePort& getSlavePort(const std::string&, - PortID = InvalidPortID) override; + Port &getPort(const std::string &if_name, PortID=InvalidPortID) override; /** * Initializes this object diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh index 69a0fb33e..4e85ac413 100644 --- a/src/mem/ruby/network/MessageBuffer.hh +++ b/src/mem/ruby/network/MessageBuffer.hh @@ -43,10 +43,12 @@ #include "base/trace.hh" #include "debug/RubyQueue.hh" +#include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Consumer.hh" +#include "mem/ruby/network/dummy_port.hh" #include "mem/ruby/slicc_interface/Message.hh" -#include "mem/packet.hh" #include "params/MessageBuffer.hh" #include "sim/sim_object.hh" @@ -120,6 +122,12 @@ class MessageBuffer : public SimObject void setIncomingLink(int link_id) { m_input_link_id = link_id; } void setVnet(int net) { m_vnet_id = net; } + Port & + getPort(const std::string &, PortID idx=InvalidPortID) override + { + return RubyDummyPort::instance(); + } + void regStats(); // Function for figuring out if any of the messages in the buffer need diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index 7f5ed2aae..4e9791824 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -60,11 +60,13 @@ #include "base/addr_range.hh" #include "base/types.hh" #include "mem/packet.hh" +#include "mem/port.hh" #include "mem/protocol/LinkDirection.hh" #include "mem/protocol/MessageSizeType.hh" #include "mem/ruby/common/MachineID.hh" #include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/Topology.hh" +#include "mem/ruby/network/dummy_port.hh" #include "params/RubyNetwork.hh" #include "sim/clocked_object.hh" @@ -132,6 +134,12 @@ class Network : public ClockedObject */ NodeID addressToNodeID(Addr addr, MachineType mtype); + Port & + getPort(const std::string &, PortID idx=InvalidPortID) override + { + return RubyDummyPort::instance(); + } + protected: // Private copy constructor and assignment operator Network(const Network& obj); diff --git a/src/mem/ruby/network/dummy_port.hh b/src/mem/ruby/network/dummy_port.hh new file mode 100644 index 000000000..ca1ef4155 --- /dev/null +++ b/src/mem/ruby/network/dummy_port.hh @@ -0,0 +1,59 @@ +/* + * Copyright 2019 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __MEM_RUBY_NETWORK_DUMMY_PORT_HH__ +#define __MEM_RUBY_NETWORK_DUMMY_PORT_HH__ + +#include "mem/port.hh" + +class RubyDummyPort : public Port +{ + public: + RubyDummyPort() : Port("DummyPort", -1) {} + + void + bind(Port &peer) override + { + // No need to connect anything here currently. MessageBuffer + // port connections only serve to print the connections in + // the config output. + // TODO: Add real ports to MessageBuffers and use MemObject connect + // code below to bind MessageBuffer senders and receivers + } + void unbind() override {} + + static RubyDummyPort & + instance() + { + static RubyDummyPort dummy; + return dummy; + } +}; + +#endif //__MEM_RUBY_NETWORK_DUMMY_PORT_HH__ diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 1327eccfb..fa1c936b7 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -229,9 +229,8 @@ AbstractController::isBlocked(Addr addr) return (m_block_map.count(addr) > 0); } -BaseMasterPort & -AbstractController::getMasterPort(const std::string &if_name, - PortID idx) +Port & +AbstractController::getPort(const std::string &if_name, PortID idx) { return memoryPort; } diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 35cd3d2a5..5e39a28d2 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer virtual void initNetQueues() = 0; /** A function used to return the port associated with this bus object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 84a70c0f1..795b473c7 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -87,53 +87,37 @@ RubyPort::init() m_mandatory_q_ptr = m_controller->getMandatoryQueue(); } -BaseMasterPort & -RubyPort::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyPort::getPort(const std::string &if_name, PortID idx) { if (if_name == "mem_master_port") { return memMasterPort; - } - - if (if_name == "pio_master_port") { + } else if (if_name == "pio_master_port") { return pioMasterPort; - } - - // used by the x86 CPUs to connect the interrupt PIO and interrupt slave - // port - if (if_name != "master") { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } else { + } else if (if_name == "mem_slave_port") { + return memSlavePort; + } else if (if_name == "pio_slave_port") { + return pioSlavePort; + } else if (if_name == "master") { + // used by the x86 CPUs to connect the interrupt PIO and interrupt + // slave port if (idx >= static_cast<PortID>(master_ports.size())) { - panic("RubyPort::getMasterPort: unknown index %d\n", idx); + panic("RubyPort::getPort master: unknown index %d\n", idx); } return *master_ports[idx]; - } -} - -BaseSlavePort & -RubyPort::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "mem_slave_port") { - return memSlavePort; - } - - if (if_name == "pio_slave_port") - return pioSlavePort; - - // used by the CPUs to connect the caches to the interconnect, and - // for the x86 case also the interrupt master - if (if_name != "slave") { - // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); - } else { + } else if (if_name == "slave") { + // used by the CPUs to connect the caches to the interconnect, and + // for the x86 case also the interrupt master if (idx >= static_cast<PortID>(slave_ports.size())) { - panic("RubyPort::getSlavePort: unknown index %d\n", idx); + panic("RubyPort::getPort slave: unknown index %d\n", idx); } return *slave_ports[idx]; } + + // pass it along to our super class + return MemObject::getPort(if_name, idx); } RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 146443282..922b3a973 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -148,10 +148,8 @@ class RubyPort : public MemObject void init() override; - BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc index e1f3a001a..438fb0e68 100644 --- a/src/mem/serial_link.cc +++ b/src/mem/serial_link.cc @@ -93,24 +93,16 @@ SerialLink::SerialLink(SerialLinkParams *p) { } -BaseMasterPort& -SerialLink::getMasterPort(const std::string &if_name, PortID idx) +Port& +SerialLink::getPort(const std::string &if_name, PortID idx) { if (if_name == "master") return masterPort; - else - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); -} - -BaseSlavePort& -SerialLink::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "slave") + else if (if_name == "slave") return slavePort; else // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh index 6315f1b94..0bb1692ed 100644 --- a/src/mem/serial_link.hh +++ b/src/mem/serial_link.hh @@ -315,10 +315,8 @@ class SerialLink : public MemObject public: - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID); virtual void init(); diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc index 64d7d204c..32fea1e89 100644 --- a/src/mem/simple_mem.cc +++ b/src/mem/simple_mem.cc @@ -231,11 +231,11 @@ SimpleMemory::recvRespRetry() dequeue(); } -BaseSlavePort & -SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) +Port & +SimpleMemory::getPort(const std::string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh index 307981b80..c8c3db516 100644 --- a/src/mem/simple_mem.hh +++ b/src/mem/simple_mem.hh @@ -187,8 +187,8 @@ class SimpleMemory : public AbstractMemory DrainState drain() override; - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void init() override; protected: diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc index b139cdc9b..247024eff 100644 --- a/src/mem/xbar.cc +++ b/src/mem/xbar.cc @@ -81,27 +81,19 @@ BaseXBar::init() { } -BaseMasterPort & -BaseXBar::getMasterPort(const std::string &if_name, PortID idx) +Port & +BaseXBar::getPort(const std::string &if_name, PortID idx) { if (if_name == "master" && idx < masterPorts.size()) { // the master port index translates directly to the vector position return *masterPorts[idx]; } else if (if_name == "default") { return *masterPorts[defaultPortID]; - } else { - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort & -BaseXBar::getSlavePort(const std::string &if_name, PortID idx) -{ - if (if_name == "slave" && idx < slavePorts.size()) { + } else if (if_name == "slave" && idx < slavePorts.size()) { // the slave port index translates directly to the vector position return *slavePorts[idx]; } else { - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh index abe2a1096..0745ea5ac 100644 --- a/src/mem/xbar.hh +++ b/src/mem/xbar.hh @@ -413,10 +413,8 @@ class BaseXBar : public MemObject virtual void init(); /** A function used to return the port associated with this object. */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID); - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; virtual void regStats(); |