diff options
Diffstat (limited to 'src/mem')
46 files changed, 928 insertions, 459 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript new file mode 100644 index 000000000..61fb766d6 --- /dev/null +++ b/src/mem/SConscript @@ -0,0 +1,46 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +Source('bridge.cc') +Source('bus.cc') +Source('dram.cc') +Source('mem_object.cc') +Source('packet.cc') +Source('physical.cc') +Source('port.cc') +Source('tport.cc') + +if env['FULL_SYSTEM']: + Source('vport.cc') +else: + Source('page_table.cc') + Source('translating_port.cc') diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 401dc0186..6e6ba2380 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -34,6 +34,8 @@ */ +#include <limits> + #include "base/misc.hh" #include "base/trace.hh" #include "mem/bus.hh" @@ -52,20 +54,30 @@ Bus::getPort(const std::string &if_name, int idx) } // if_name ignored? forced to be empty? - int id = interfaces.size(); + int id = maxId++; + assert(maxId < std::numeric_limits<typeof(maxId)>::max()); BusPort *bp = new BusPort(csprintf("%s-p%d", name(), id), this, id); - interfaces.push_back(bp); + interfaces[id] = bp; return bp; } +void +Bus::deletePortRefs(Port *p) +{ + BusPort *bp = dynamic_cast<BusPort*>(p); + if (bp == NULL) + panic("Couldn't convert Port* to BusPort*\n"); + interfaces.erase(bp->getId()); +} + /** Get the ranges of anyone other buses that we are connected to. */ void Bus::init() { - std::vector<BusPort*>::iterator intIter; + m5::hash_map<short,BusPort*>::iterator intIter; for (intIter = interfaces.begin(); intIter != interfaces.end(); intIter++) - (*intIter)->sendStatusChange(Port::RangeChange); + intIter->second->sendStatusChange(Port::RangeChange); } Bus::BusFreeEvent::BusFreeEvent(Bus *_bus) : Event(&mainEventQueue), bus(_bus) @@ -184,12 +196,13 @@ Bus::recvTiming(PacketPtr pkt) } } else { //Snoop didn't succeed - DPRINTF(Bus, "Adding a retry to RETRY list %i\n", pktPort); + DPRINTF(Bus, "Adding a retry to RETRY list %d\n", + pktPort->getId()); addToRetryList(pktPort); return false; } } else { - assert(dest >= 0 && dest < interfaces.size()); + assert(dest >= 0 && dest < maxId); assert(dest != pkt->getSrc()); // catch infinite loops port = interfaces[dest]; } @@ -201,7 +214,8 @@ Bus::recvTiming(PacketPtr pkt) // Packet was successfully sent. Return true. // Also take care of retries if (inRetry) { - DPRINTF(Bus, "Remove retry from list %i\n", retryList.front()); + DPRINTF(Bus, "Remove retry from list %d\n", + retryList.front()->getId()); retryList.front()->onRetryList(false); retryList.pop_front(); inRetry = false; @@ -210,7 +224,8 @@ Bus::recvTiming(PacketPtr pkt) } // Packet not successfully sent. Leave or put it on the retry list. - DPRINTF(Bus, "Adding a retry to RETRY list %i\n", pktPort); + DPRINTF(Bus, "Adding a retry to RETRY list %d\n", + pktPort->getId()); addToRetryList(pktPort); return false; } @@ -436,7 +451,6 @@ Bus::recvStatusChange(Port::Status status, int id) { AddrRangeList ranges; AddrRangeList snoops; - int x; AddrRangeIter iter; assert(status == Port::RangeChange && @@ -458,7 +472,7 @@ Bus::recvStatusChange(Port::Status status, int id) } } else { - assert((id < interfaces.size() && id >= 0) || id == defaultId); + assert((id < maxId && id >= 0) || id == defaultId); Port *port = interfaces[id]; range_map<Addr,int>::iterator portIter; std::vector<DevMap>::iterator snoopIter; @@ -503,9 +517,11 @@ Bus::recvStatusChange(Port::Status status, int id) // tell all our peers that our address range has changed. // Don't tell the device that caused this change, it already knows - for (x = 0; x < interfaces.size(); x++) - if (x != id) - interfaces[x]->sendStatusChange(Port::RangeChange); + m5::hash_map<short,BusPort*>::iterator intIter; + + for (intIter = interfaces.begin(); intIter != interfaces.end(); intIter++) + if (intIter->first != id) + intIter->second->sendStatusChange(Port::RangeChange); if (id != defaultId && defaultPort) defaultPort->sendStatusChange(Port::RangeChange); diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 0ad4aad60..6706b6c77 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -42,6 +42,7 @@ #include <inttypes.h> #include "base/range.hh" +#include "base/hashmap.hh" #include "base/range_map.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" @@ -156,6 +157,8 @@ class Bus : public MemObject void onRetryList(bool newVal) { _onRetryList = newVal; } + int getId() { return id; } + protected: /** When reciving a timing request from the peer port (at id), @@ -210,9 +213,12 @@ class Bus : public MemObject bool inRetry; + /** max number of bus ids we've handed out so far */ + short maxId; + /** An array of pointers to the peer port interfaces connected to this bus.*/ - std::vector<BusPort*> interfaces; + m5::hash_map<short,BusPort*> interfaces; /** An array of pointers to ports that retry should be called on because the * original send failed for whatever reason.*/ @@ -250,6 +256,7 @@ class Bus : public MemObject /** A function used to return the port associated with this bus object. */ virtual Port *getPort(const std::string &if_name, int idx = -1); + virtual void deletePortRefs(Port *p); virtual void init(); @@ -259,7 +266,7 @@ class Bus : public MemObject bool responder_set) : MemObject(n), busId(bus_id), clock(_clock), width(_width), tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false), - defaultPort(NULL), responderSet(responder_set) + maxId(0), defaultPort(NULL), responderSet(responder_set) { //Both the width and clock period must be positive if (width <= 0) diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript new file mode 100644 index 000000000..7150719ad --- /dev/null +++ b/src/mem/cache/SConscript @@ -0,0 +1,35 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +Source('base_cache.cc') +Source('cache.cc') +Source('cache_builder.cc') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index d9e6c5e1f..ed665dafb 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -356,7 +356,7 @@ BaseCache::CacheEvent::process() const char * BaseCache::CacheEvent::description() { - return "timing event\n"; + return "BaseCache timing event"; } void @@ -370,17 +370,12 @@ BaseCache::init() void BaseCache::regStats() { - Request temp_req((Addr) NULL, 4, 0); - Packet::Command temp_cmd = Packet::ReadReq; - Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary - temp_pkt.allocate(); //Temp allocate, all need data - using namespace Stats; // Hit statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); hits[access_idx] .init(maxThreadsPerCPU) @@ -395,20 +390,20 @@ BaseCache::regStats() .desc("number of demand (read+write) hits") .flags(total) ; - demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq]; + demandHits = hits[MemCmd::ReadReq] + hits[MemCmd::WriteReq]; overallHits .name(name() + ".overall_hits") .desc("number of overall hits") .flags(total) ; - overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq] - + hits[Packet::Writeback]; + overallHits = demandHits + hits[MemCmd::SoftPFReq] + hits[MemCmd::HardPFReq] + + hits[MemCmd::Writeback]; // Miss statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); misses[access_idx] .init(maxThreadsPerCPU) @@ -423,20 +418,20 @@ BaseCache::regStats() .desc("number of demand (read+write) misses") .flags(total) ; - demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq]; + demandMisses = misses[MemCmd::ReadReq] + misses[MemCmd::WriteReq]; overallMisses .name(name() + ".overall_misses") .desc("number of overall misses") .flags(total) ; - overallMisses = demandMisses + misses[Packet::SoftPFReq] + - misses[Packet::HardPFReq] + misses[Packet::Writeback]; + overallMisses = demandMisses + misses[MemCmd::SoftPFReq] + + misses[MemCmd::HardPFReq] + misses[MemCmd::Writeback]; // Miss latency statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); missLatency[access_idx] .init(maxThreadsPerCPU) @@ -451,20 +446,20 @@ BaseCache::regStats() .desc("number of demand (read+write) miss cycles") .flags(total) ; - demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq]; + demandMissLatency = missLatency[MemCmd::ReadReq] + missLatency[MemCmd::WriteReq]; overallMissLatency .name(name() + ".overall_miss_latency") .desc("number of overall miss cycles") .flags(total) ; - overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] + - missLatency[Packet::HardPFReq]; + overallMissLatency = demandMissLatency + missLatency[MemCmd::SoftPFReq] + + missLatency[MemCmd::HardPFReq]; // access formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); accesses[access_idx] .name(name() + "." + cstr + "_accesses") @@ -490,9 +485,9 @@ BaseCache::regStats() overallAccesses = overallHits + overallMisses; // miss rate formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); missRate[access_idx] .name(name() + "." + cstr + "_miss_rate") @@ -518,9 +513,9 @@ BaseCache::regStats() overallMissRate = overallMisses / overallAccesses; // miss latency formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); avgMissLatency[access_idx] .name(name() + "." + cstr + "_avg_miss_latency") diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index c10d98e8e..ee871c1c4 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -200,14 +200,14 @@ class BaseCache : public MemObject */ /** Number of hits per thread for each type of command. @sa Packet::Command */ - Stats::Vector<> hits[NUM_MEM_CMDS]; + Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS]; /** Number of hits for demand accesses. */ Stats::Formula demandHits; /** Number of hit for all accesses. */ Stats::Formula overallHits; /** Number of misses per thread for each type of command. @sa Packet::Command */ - Stats::Vector<> misses[NUM_MEM_CMDS]; + Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS]; /** Number of misses for demand accesses. */ Stats::Formula demandMisses; /** Number of misses for all accesses. */ @@ -217,28 +217,28 @@ class BaseCache : public MemObject * Total number of cycles per thread/command spent waiting for a miss. * Used to calculate the average miss latency. */ - Stats::Vector<> missLatency[NUM_MEM_CMDS]; + Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS]; /** Total number of cycles spent waiting for demand misses. */ Stats::Formula demandMissLatency; /** Total number of cycles spent waiting for all misses. */ Stats::Formula overallMissLatency; /** The number of accesses per command and thread. */ - Stats::Formula accesses[NUM_MEM_CMDS]; + Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; /** The number of demand accesses. */ Stats::Formula demandAccesses; /** The number of overall accesses. */ Stats::Formula overallAccesses; /** The miss rate per command and thread. */ - Stats::Formula missRate[NUM_MEM_CMDS]; + Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; /** The miss rate of all demand accesses. */ Stats::Formula demandMissRate; /** The miss rate for all accesses. */ Stats::Formula overallMissRate; /** The average miss latency per command and thread. */ - Stats::Formula avgMissLatency[NUM_MEM_CMDS]; + Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; /** The average miss latency for demand misses. */ Stats::Formula demandAvgMissLatency; /** The average miss latency for all misses. */ @@ -535,7 +535,7 @@ class BaseCache : public MemObject } } else { - if (pkt->cmd != Packet::UpgradeReq) + if (pkt->cmd != MemCmd::UpgradeReq) { delete pkt->req; delete pkt; @@ -594,7 +594,7 @@ class BaseCache : public MemObject } } else { - if (pkt->cmd != Packet::UpgradeReq) + if (pkt->cmd != MemCmd::UpgradeReq) { delete pkt->req; delete pkt; diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 26dab2179..722ce216b 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -331,6 +331,7 @@ class Cache : public BaseCache Cache(const std::string &_name, Params ¶ms); virtual Port *getPort(const std::string &if_name, int idx = -1); + virtual void deletePortRefs(Port *p); virtual void recvStatusChange(Port::Status status, bool isCpuSide); diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh index 7b999e4b1..fa00a0f5a 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/cache_blk.hh @@ -37,7 +37,7 @@ #include <list> -#include "sim/root.hh" // for Tick +#include "sim/core.hh" // for Tick #include "arch/isa_traits.hh" // for Addr #include "mem/request.hh" @@ -249,7 +249,7 @@ class CacheBlk } } - req->setScResult(success ? 1 : 0); + req->setExtraData(success ? 1 : 0); clearLoadLocks(); return success; } else { diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 08e226343..fc4660269 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -90,7 +90,7 @@ Cache(const std::string &_name, coherence->setCache(this); prefetcher->setCache(this); invalidateReq = new Request((Addr) NULL, blkSize, 0); - invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0); + invalidatePkt = new Packet(invalidateReq, MemCmd::InvalidateReq, 0); } template<class TagStore, class Coherence> @@ -206,7 +206,7 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat, // complete miss (no matching block) if (pkt->req->isLocked() && pkt->isWrite()) { // miss on store conditional... just give up now - pkt->req->setScResult(0); + pkt->req->setExtraData(0); pkt->flags |= SATISFIED; } } @@ -239,7 +239,7 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, PacketPtr &pkt, target->flags |= SATISFIED; - if (target->cmd == Packet::InvalidateReq) { + if (target->cmd == MemCmd::InvalidateReq) { tags->invalidateBlk(blk); blk = NULL; } @@ -316,7 +316,7 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, MSHR * mshr, Tick completion_time = tags->getHitLatency() + transfer_offset ? pkt->finishTime : pkt->firstWordTime; - if (target->cmd == Packet::InvalidateReq) { + if (target->cmd == MemCmd::InvalidateReq) { //Mark the blk as invalid now, if it hasn't been already if (blk) { tags->invalidateBlk(blk); @@ -430,7 +430,7 @@ Cache<TagStore,Coherence>::writebackBlk(BlkType *blk) Request *writebackReq = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0); - PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1); + PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1); writeback->allocate(); std::memcpy(writeback->getPtr<uint8_t>(),blk->data,blkSize); @@ -560,11 +560,11 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt) /** @todo make the fast write alloc (wh64) work with coherence. */ /** @todo Do we want to do fast writes for writebacks as well? */ if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() && - (pkt->cmd == Packet::WriteReq - || pkt->cmd == Packet::WriteInvalidateReq) ) { + (pkt->cmd == MemCmd::WriteReq + || pkt->cmd == MemCmd::WriteInvalidateReq) ) { // not outstanding misses, can do this MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr()); - if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) { + if (pkt->cmd == MemCmd::WriteInvalidateReq || !outstanding_miss) { if (outstanding_miss) { warn("WriteInv doing a fastallocate" "with an outstanding miss to the same address\n"); @@ -575,8 +575,10 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt) } } while (!writebacks.empty()) { - missQueue->doWriteback(writebacks.front()); + PacketPtr wbPkt = writebacks.front(); + missQueue->doWriteback(wbPkt); writebacks.pop_front(); + delete wbPkt; } DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(), @@ -586,12 +588,7 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt) // Hit hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; // clear dirty bit if write through - if (pkt->needsResponse()) - respond(pkt, curTick+lat); - if (pkt->cmd == Packet::Writeback) { - //Signal that you can kill the pkt/req - pkt->flags |= SATISFIED; - } + respond(pkt, curTick+lat); return true; } @@ -609,14 +606,14 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt) if (pkt->flags & SATISFIED) { // happens when a store conditional fails because it missed // the cache completely - if (pkt->needsResponse()) - respond(pkt, curTick+lat); + respond(pkt, curTick+lat); } else { missQueue->handleMiss(pkt, size, curTick + hitLatency); } - if (pkt->cmd == Packet::Writeback) { + if (!pkt->needsResponse()) { //Need to clean up the packet on a writeback miss, but leave the request + //for the next level. delete pkt; } @@ -632,11 +629,11 @@ Cache<TagStore,Coherence>::getPacket() PacketPtr pkt = missQueue->getPacket(); if (pkt) { if (!pkt->req->isUncacheable()) { - if (pkt->cmd == Packet::HardPFReq) - misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++; + if (pkt->cmd == MemCmd::HardPFReq) + misses[MemCmd::HardPFReq][0/*pkt->req->getThreadNum()*/]++; BlkType *blk = tags->findBlock(pkt->getAddr()); - Packet::Command cmd = coherence->getBusCmd(pkt->cmd, - (blk)? blk->status : 0); + MemCmd cmd = + coherence->getBusCmd(pkt->cmd, (blk) ? blk->status : 0); missQueue->setBusCmd(pkt, cmd); } } @@ -655,7 +652,7 @@ Cache<TagStore,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, if (success && !(SIGNAL_NACK_HACK)) { //Remember if it was an upgrade because writeback MSHR's are removed //in Mark in Service - bool upgrade = (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq); + bool upgrade = (mshr->pkt && mshr->pkt->cmd == MemCmd::UpgradeReq); missQueue->markInService(mshr->pkt, mshr); @@ -726,8 +723,10 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt) blk = handleFill(blk, (MSHR*)pkt->senderState, new_state, writebacks, pkt); while (!writebacks.empty()) { - missQueue->doWriteback(writebacks.front()); - writebacks.pop_front(); + PacketPtr wbPkt = writebacks.front(); + missQueue->doWriteback(wbPkt); + writebacks.pop_front(); + delete wbPkt; } } missQueue->handleResponse(pkt, curTick + hitLatency); @@ -780,8 +779,8 @@ Cache<TagStore,Coherence>::snoop(PacketPtr &pkt) if (mshr) { if (mshr->inService) { if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill()) - && (pkt->cmd != Packet::InvalidateReq - && pkt->cmd != Packet::WriteInvalidateReq)) { + && (pkt->cmd != MemCmd::InvalidateReq + && pkt->cmd != MemCmd::WriteInvalidateReq)) { //If the outstanding request was an invalidate //(upgrade,readex,..) Then we need to ACK the request //until we get the data Also NACK if the outstanding @@ -987,11 +986,11 @@ Cache<TagStore,Coherence>::probe(PacketPtr &pkt, bool update, panic("Atomic access ran into outstanding MSHR's or WB's!"); } if (!pkt->req->isUncacheable() /*Uncacheables just go through*/ - && (pkt->cmd != Packet::Writeback)/*Writebacks on miss fall through*/) { + && (pkt->cmd != MemCmd::Writeback)/*Writebacks on miss fall through*/) { // Fetch the cache block to fill BlkType *blk = tags->findBlock(pkt->getAddr()); - Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd, - (blk)? blk->status : 0); + MemCmd temp_cmd = + coherence->getBusCmd(pkt->cmd, (blk) ? blk->status : 0); PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize); @@ -1045,8 +1044,10 @@ return 0; // There was a cache hit. // Handle writebacks if needed while (!writebacks.empty()){ - memSidePort->sendAtomic(writebacks.front()); + PacketPtr wbPkt = writebacks.front(); + memSidePort->sendAtomic(wbPkt); writebacks.pop_front(); + delete wbPkt; } hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; @@ -1105,7 +1106,7 @@ Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx) } else if (if_name == "functional") { - return new CpuSidePort(name() + "-cpu_side_port", this); + return new CpuSidePort(name() + "-cpu_side_funcport", this); } else if (if_name == "cpu_side") { @@ -1126,6 +1127,15 @@ Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx) else panic("Port name %s unrecognized\n", if_name); } +template<class TagStore, class Coherence> +void +Cache<TagStore,Coherence>::deletePortRefs(Port *p) +{ + if (cpuSidePort == p || memSidePort == p) + panic("Can only delete functional ports\n"); + // nothing else to do +} + template<class TagStore, class Coherence> bool @@ -1152,7 +1162,7 @@ Cache<TagStore,Coherence>::CpuSidePort::recvTiming(PacketPtr pkt) } if (pkt->isWrite() && (pkt->req->isLocked())) { - pkt->req->setScResult(1); + pkt->req->setExtraData(1); } myCache()->access(pkt); return true; diff --git a/src/mem/cache/coherence/SConscript b/src/mem/cache/coherence/SConscript new file mode 100644 index 000000000..03a2d85d7 --- /dev/null +++ b/src/mem/cache/coherence/SConscript @@ -0,0 +1,35 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +Source('coherence_protocol.cc') +Source('uni_coherence.cc') + diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc index 3d7721805..e8520401d 100644 --- a/src/mem/cache/coherence/coherence_protocol.cc +++ b/src/mem/cache/coherence/coherence_protocol.cc @@ -47,7 +47,7 @@ using namespace std; CoherenceProtocol::StateTransition::StateTransition() - : busCmd(Packet::InvalidCmd), newState(-1), snoopFunc(invalidTransition) + : busCmd(MemCmd::InvalidCmd), newState(-1), snoopFunc(invalidTransition) { } @@ -59,132 +59,132 @@ CoherenceProtocol::regStats() // requestCount and snoopCount arrays, most of these are invalid, // so we just select the interesting ones to print here. - requestCount[Invalid][Packet::ReadReq] + requestCount[Invalid][MemCmd::ReadReq] .name(name() + ".read_invalid") .desc("read misses to invalid blocks") ; - requestCount[Invalid][Packet::WriteReq] + requestCount[Invalid][MemCmd::WriteReq] .name(name() +".write_invalid") .desc("write misses to invalid blocks") ; - requestCount[Invalid][Packet::SoftPFReq] + requestCount[Invalid][MemCmd::SoftPFReq] .name(name() +".swpf_invalid") .desc("soft prefetch misses to invalid blocks") ; - requestCount[Invalid][Packet::HardPFReq] + requestCount[Invalid][MemCmd::HardPFReq] .name(name() +".hwpf_invalid") .desc("hard prefetch misses to invalid blocks") ; - requestCount[Shared][Packet::WriteReq] + requestCount[Shared][MemCmd::WriteReq] .name(name() + ".write_shared") .desc("write misses to shared blocks") ; - requestCount[Owned][Packet::WriteReq] + requestCount[Owned][MemCmd::WriteReq] .name(name() + ".write_owned") .desc("write misses to owned blocks") ; - snoopCount[Shared][Packet::ReadReq] + snoopCount[Shared][MemCmd::ReadReq] .name(name() + ".snoop_read_shared") .desc("read snoops on shared blocks") ; - snoopCount[Shared][Packet::ReadExReq] + snoopCount[Shared][MemCmd::ReadExReq] .name(name() + ".snoop_readex_shared") .desc("readEx snoops on shared blocks") ; - snoopCount[Shared][Packet::UpgradeReq] + snoopCount[Shared][MemCmd::UpgradeReq] .name(name() + ".snoop_upgrade_shared") .desc("upgradee snoops on shared blocks") ; - snoopCount[Modified][Packet::ReadReq] + snoopCount[Modified][MemCmd::ReadReq] .name(name() + ".snoop_read_modified") .desc("read snoops on modified blocks") ; - snoopCount[Modified][Packet::ReadExReq] + snoopCount[Modified][MemCmd::ReadExReq] .name(name() + ".snoop_readex_modified") .desc("readEx snoops on modified blocks") ; - snoopCount[Owned][Packet::ReadReq] + snoopCount[Owned][MemCmd::ReadReq] .name(name() + ".snoop_read_owned") .desc("read snoops on owned blocks") ; - snoopCount[Owned][Packet::ReadExReq] + snoopCount[Owned][MemCmd::ReadExReq] .name(name() + ".snoop_readex_owned") .desc("readEx snoops on owned blocks") ; - snoopCount[Owned][Packet::UpgradeReq] + snoopCount[Owned][MemCmd::UpgradeReq] .name(name() + ".snoop_upgrade_owned") .desc("upgrade snoops on owned blocks") ; - snoopCount[Exclusive][Packet::ReadReq] + snoopCount[Exclusive][MemCmd::ReadReq] .name(name() + ".snoop_read_exclusive") .desc("read snoops on exclusive blocks") ; - snoopCount[Exclusive][Packet::ReadExReq] + snoopCount[Exclusive][MemCmd::ReadExReq] .name(name() + ".snoop_readex_exclusive") .desc("readEx snoops on exclusive blocks") ; - snoopCount[Shared][Packet::InvalidateReq] + snoopCount[Shared][MemCmd::InvalidateReq] .name(name() + ".snoop_inv_shared") .desc("Invalidate snoops on shared blocks") ; - snoopCount[Owned][Packet::InvalidateReq] + snoopCount[Owned][MemCmd::InvalidateReq] .name(name() + ".snoop_inv_owned") .desc("Invalidate snoops on owned blocks") ; - snoopCount[Exclusive][Packet::InvalidateReq] + snoopCount[Exclusive][MemCmd::InvalidateReq] .name(name() + ".snoop_inv_exclusive") .desc("Invalidate snoops on exclusive blocks") ; - snoopCount[Modified][Packet::InvalidateReq] + snoopCount[Modified][MemCmd::InvalidateReq] .name(name() + ".snoop_inv_modified") .desc("Invalidate snoops on modified blocks") ; - snoopCount[Invalid][Packet::InvalidateReq] + snoopCount[Invalid][MemCmd::InvalidateReq] .name(name() + ".snoop_inv_invalid") .desc("Invalidate snoops on invalid blocks") ; - snoopCount[Shared][Packet::WriteInvalidateReq] + snoopCount[Shared][MemCmd::WriteInvalidateReq] .name(name() + ".snoop_writeinv_shared") .desc("WriteInvalidate snoops on shared blocks") ; - snoopCount[Owned][Packet::WriteInvalidateReq] + snoopCount[Owned][MemCmd::WriteInvalidateReq] .name(name() + ".snoop_writeinv_owned") .desc("WriteInvalidate snoops on owned blocks") ; - snoopCount[Exclusive][Packet::WriteInvalidateReq] + snoopCount[Exclusive][MemCmd::WriteInvalidateReq] .name(name() + ".snoop_writeinv_exclusive") .desc("WriteInvalidate snoops on exclusive blocks") ; - snoopCount[Modified][Packet::WriteInvalidateReq] + snoopCount[Modified][MemCmd::WriteInvalidateReq] .name(name() + ".snoop_writeinv_modified") .desc("WriteInvalidate snoops on modified blocks") ; - snoopCount[Invalid][Packet::WriteInvalidateReq] + snoopCount[Invalid][MemCmd::WriteInvalidateReq] .name(name() + ".snoop_writeinv_invalid") .desc("WriteInvalidate snoops on invalid blocks") ; @@ -278,11 +278,13 @@ CoherenceProtocol::CoherenceProtocol(const string &name, } // set up a few shortcuts to save typing & visual clutter - typedef Packet P; - StateTransition (&tt)[stateMax+1][NUM_MEM_CMDS] = transitionTable; + typedef MemCmd MC; + StateTransition (&tt)[stateMax+1][MC::NUM_MEM_CMDS] = transitionTable; - P::Command writeToSharedCmd = doUpgrades ? P::UpgradeReq : P::ReadExReq; - P::Command writeToSharedResp = doUpgrades ? P::UpgradeReq : P::ReadExResp; + MC::Command writeToSharedCmd = + doUpgrades ? MC::UpgradeReq : MC::ReadExReq; + MC::Command writeToSharedResp = + doUpgrades ? MC::UpgradeReq : MC::ReadExResp; // Note that all transitions by default cause a panic. // Override the valid transitions with the appropriate actions here. @@ -290,34 +292,34 @@ CoherenceProtocol::CoherenceProtocol(const string &name, // // ----- incoming requests: specify outgoing bus request ----- // - tt[Invalid][P::ReadReq].onRequest(P::ReadReq); + tt[Invalid][MC::ReadReq].onRequest(MC::ReadReq); // we only support write allocate right now - tt[Invalid][P::WriteReq].onRequest(P::ReadExReq); - tt[Shared][P::WriteReq].onRequest(writeToSharedCmd); + tt[Invalid][MC::WriteReq].onRequest(MC::ReadExReq); + tt[Shared][MC::WriteReq].onRequest(writeToSharedCmd); if (hasOwned) { - tt[Owned][P::WriteReq].onRequest(writeToSharedCmd); + tt[Owned][MC::WriteReq].onRequest(writeToSharedCmd); } // Prefetching causes a read - tt[Invalid][P::SoftPFReq].onRequest(P::ReadReq); - tt[Invalid][P::HardPFReq].onRequest(P::ReadReq); + tt[Invalid][MC::SoftPFReq].onRequest(MC::ReadReq); + tt[Invalid][MC::HardPFReq].onRequest(MC::ReadReq); // // ----- on response to given request: specify new state ----- // - tt[Invalid][P::ReadExResp].onResponse(Modified); + tt[Invalid][MC::ReadExResp].onResponse(Modified); tt[Shared][writeToSharedResp].onResponse(Modified); // Go to Exclusive state on read response if we have one (will // move into shared if the shared line is asserted in the // getNewState function) // // originally had this as: - // tt[Invalid][P::ReadResp].onResponse(hasExclusive ? Exclusive: Shared); + // tt[Invalid][MC::ReadResp].onResponse(hasExclusive ? Exclusive: Shared); // ...but for some reason that caused a link error... if (hasExclusive) { - tt[Invalid][P::ReadResp].onResponse(Exclusive); + tt[Invalid][MC::ReadResp].onResponse(Exclusive); } else { - tt[Invalid][P::ReadResp].onResponse(Shared); + tt[Invalid][MC::ReadResp].onResponse(Shared); } if (hasOwned) { tt[Owned][writeToSharedResp].onResponse(Modified); @@ -326,58 +328,58 @@ CoherenceProtocol::CoherenceProtocol(const string &name, // // ----- bus snoop transition functions ----- // - tt[Invalid][P::ReadReq].onSnoop(nullTransition); - tt[Invalid][P::ReadExReq].onSnoop(nullTransition); - tt[Invalid][P::InvalidateReq].onSnoop(invalidateTrans); - tt[Invalid][P::WriteInvalidateReq].onSnoop(invalidateTrans); - tt[Shared][P::ReadReq].onSnoop(hasExclusive + tt[Invalid][MC::ReadReq].onSnoop(nullTransition); + tt[Invalid][MC::ReadExReq].onSnoop(nullTransition); + tt[Invalid][MC::InvalidateReq].onSnoop(invalidateTrans); + tt[Invalid][MC::WriteInvalidateReq].onSnoop(invalidateTrans); + tt[Shared][MC::ReadReq].onSnoop(hasExclusive ? assertShared : nullTransition); - tt[Shared][P::ReadExReq].onSnoop(invalidateTrans); - tt[Shared][P::InvalidateReq].onSnoop(invalidateTrans); - tt[Shared][P::WriteInvalidateReq].onSnoop(invalidateTrans); + tt[Shared][MC::ReadExReq].onSnoop(invalidateTrans); + tt[Shared][MC::InvalidateReq].onSnoop(invalidateTrans); + tt[Shared][MC::WriteInvalidateReq].onSnoop(invalidateTrans); if (doUpgrades) { - tt[Invalid][P::UpgradeReq].onSnoop(nullTransition); - tt[Shared][P::UpgradeReq].onSnoop(invalidateTrans); + tt[Invalid][MC::UpgradeReq].onSnoop(nullTransition); + tt[Shared][MC::UpgradeReq].onSnoop(invalidateTrans); } - tt[Modified][P::ReadExReq].onSnoop(supplyAndInvalidateTrans); - tt[Modified][P::ReadReq].onSnoop(hasOwned + tt[Modified][MC::ReadExReq].onSnoop(supplyAndInvalidateTrans); + tt[Modified][MC::ReadReq].onSnoop(hasOwned ? supplyAndGotoOwnedTrans : supplyAndGotoSharedTrans); - tt[Modified][P::InvalidateReq].onSnoop(invalidateTrans); - tt[Modified][P::WriteInvalidateReq].onSnoop(invalidateTrans); + tt[Modified][MC::InvalidateReq].onSnoop(invalidateTrans); + tt[Modified][MC::WriteInvalidateReq].onSnoop(invalidateTrans); if (hasExclusive) { - tt[Exclusive][P::ReadReq].onSnoop(assertShared); - tt[Exclusive][P::ReadExReq].onSnoop(invalidateTrans); - tt[Exclusive][P::InvalidateReq].onSnoop(invalidateTrans); - tt[Exclusive][P::WriteInvalidateReq].onSnoop(invalidateTrans); + tt[Exclusive][MC::ReadReq].onSnoop(assertShared); + tt[Exclusive][MC::ReadExReq].onSnoop(invalidateTrans); + tt[Exclusive][MC::InvalidateReq].onSnoop(invalidateTrans); + tt[Exclusive][MC::WriteInvalidateReq].onSnoop(invalidateTrans); } if (hasOwned) { - tt[Owned][P::ReadReq].onSnoop(supplyAndGotoOwnedTrans); - tt[Owned][P::ReadExReq].onSnoop(supplyAndInvalidateTrans); - tt[Owned][P::UpgradeReq].onSnoop(invalidateTrans); - tt[Owned][P::InvalidateReq].onSnoop(invalidateTrans); - tt[Owned][P::WriteInvalidateReq].onSnoop(invalidateTrans); + tt[Owned][MC::ReadReq].onSnoop(supplyAndGotoOwnedTrans); + tt[Owned][MC::ReadExReq].onSnoop(supplyAndInvalidateTrans); + tt[Owned][MC::UpgradeReq].onSnoop(invalidateTrans); + tt[Owned][MC::InvalidateReq].onSnoop(invalidateTrans); + tt[Owned][MC::WriteInvalidateReq].onSnoop(invalidateTrans); } // @todo add in hardware prefetch to this list } -Packet::Command -CoherenceProtocol::getBusCmd(Packet::Command cmdIn, CacheBlk::State state, +MemCmd +CoherenceProtocol::getBusCmd(MemCmd cmdIn, CacheBlk::State state, MSHR *mshr) { state &= stateMask; - int cmd_idx = (int) cmdIn; + int cmd_idx = cmdIn.toInt(); assert(0 <= state && state <= stateMax); - assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS); + assert(0 <= cmd_idx && cmd_idx < MemCmd::NUM_MEM_CMDS); - Packet::Command cmdOut = transitionTable[state][cmd_idx].busCmd; + MemCmd::Command cmdOut = transitionTable[state][cmd_idx].busCmd; - assert(cmdOut != Packet::InvalidCmd); + assert(cmdOut != MemCmd::InvalidCmd); ++requestCount[state][cmd_idx]; @@ -392,7 +394,7 @@ CoherenceProtocol::getNewState(PacketPtr &pkt, CacheBlk::State oldState) int cmd_idx = pkt->cmdToIndex(); assert(0 <= state && state <= stateMax); - assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS); + assert(0 <= cmd_idx && cmd_idx < MemCmd::NUM_MEM_CMDS); CacheBlk::State newState = transitionTable[state][cmd_idx].newState; @@ -425,7 +427,7 @@ CoherenceProtocol::handleBusRequest(BaseCache *cache, PacketPtr &pkt, int cmd_idx = pkt->cmdToIndex(); assert(0 <= state && state <= stateMax); - assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS); + assert(0 <= cmd_idx && cmd_idx < MemCmd::NUM_MEM_CMDS); // assert(mshr == NULL); // can't currently handle outstanding requests //Check first if MSHR, and also insure, if there is one, that it is not in service diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh index 481277523..775bc807a 100644 --- a/src/mem/cache/coherence/coherence_protocol.hh +++ b/src/mem/cache/coherence/coherence_protocol.hh @@ -80,8 +80,8 @@ class CoherenceProtocol : public SimObject * @param mshr The MSHR matching the request. * @return The proper bus command, as determined by the protocol. */ - Packet::Command getBusCmd(Packet::Command cmd, CacheBlk::State status, - MSHR *mshr = NULL); + MemCmd getBusCmd(MemCmd cmd, CacheBlk::State status, + MSHR *mshr = NULL); /** * Return the proper state given the current state and the bus response. @@ -235,7 +235,7 @@ class CoherenceProtocol : public SimObject * The table of all possible transitions, organized by starting state and * request command. */ - StateTransition transitionTable[stateMax+1][NUM_MEM_CMDS]; + StateTransition transitionTable[stateMax+1][MemCmd::NUM_MEM_CMDS]; /** * @addtogroup CoherenceStatistics @@ -244,11 +244,11 @@ class CoherenceProtocol : public SimObject /** * State accesses from parent cache. */ - Stats::Scalar<> requestCount[stateMax+1][NUM_MEM_CMDS]; + Stats::Scalar<> requestCount[stateMax+1][MemCmd::NUM_MEM_CMDS]; /** * State accesses from snooped requests. */ - Stats::Scalar<> snoopCount[stateMax+1][NUM_MEM_CMDS]; + Stats::Scalar<> snoopCount[stateMax+1][MemCmd::NUM_MEM_CMDS]; /** * @} */ diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh index a1fd33080..1c89c703a 100644 --- a/src/mem/cache/coherence/simple_coherence.hh +++ b/src/mem/cache/coherence/simple_coherence.hh @@ -131,7 +131,7 @@ class SimpleCoherence //Got rid of, there could be an MSHR, but it can't be in service if (blk != NULL) { - if (pkt->cmd != Packet::Writeback) { + if (pkt->cmd != MemCmd::Writeback) { return protocol->handleBusRequest(cache, pkt, blk, mshr, new_state); } @@ -148,9 +148,10 @@ class SimpleCoherence * @param state The current state of the cache block. * @return The proper bus command, as determined by the protocol. */ - Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state) + MemCmd getBusCmd(MemCmd cmd, + CacheBlk::State state) { - if (cmd == Packet::Writeback) return Packet::Writeback; + if (cmd == MemCmd::Writeback) return MemCmd::Writeback; return protocol->getBusCmd(cmd, state); } diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index ea615d70a..6061c89c3 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -99,19 +99,19 @@ UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) if (isTiming) { // Forward to other caches Request* req = new Request(pkt->req->getPaddr(), pkt->getSize(), 0); - PacketPtr tmp = new Packet(req, Packet::InvalidateReq, -1); + PacketPtr tmp = new Packet(req, MemCmd::InvalidateReq, -1); cshrs.allocate(tmp); cache->setSlaveRequest(Request_Coherence, curTick); if (cshrs.isFull()) cache->setBlockedForSnoop(Blocked_Coherence); } else { - PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); + PacketPtr tmp = new Packet(pkt->req, MemCmd::InvalidateReq, -1); cache->cpuSidePort->sendAtomic(tmp); delete tmp; } /**/ -/* PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); +/* PacketPtr tmp = new Packet(pkt->req, MemCmd::InvalidateReq, -1); cache->cpuSidePort->sendFunctional(tmp); delete tmp; */ @@ -119,7 +119,7 @@ UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) if (pkt->isRead()) { /*For now we will see if someone above us has the data by doing a functional access on reads. Fix this later */ - PacketPtr tmp = new Packet(pkt->req, Packet::ReadReq, -1); + PacketPtr tmp = new Packet(pkt->req, MemCmd::ReadReq, -1); tmp->allocate(); cache->cpuSidePort->sendFunctional(tmp); bool hit = (tmp->result == Packet::Success); diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh index 9a4aacdec..9efb4e192 100644 --- a/src/mem/cache/coherence/uni_coherence.hh +++ b/src/mem/cache/coherence/uni_coherence.hh @@ -77,13 +77,13 @@ class UniCoherence * @return The proper bus command, as determined by the protocol. * @todo Make changes so writebacks don't get here. */ - Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state) + MemCmd getBusCmd(MemCmd cmd, CacheBlk::State state) { - if (cmd == Packet::HardPFReq && state) + if (cmd == MemCmd::HardPFReq && state) warn("Trying to issue a prefetch to a block we already have\n"); - if (cmd == Packet::Writeback) - return Packet::Writeback; - return Packet::ReadReq; + if (cmd == MemCmd::Writeback) + return MemCmd::Writeback; + return MemCmd::ReadReq; } /** @@ -96,7 +96,7 @@ class UniCoherence { if (pkt->senderState) //Blocking Buffers don't get mshrs { - if (((MSHR *)(pkt->senderState))->originalCmd == Packet::HardPFReq) { + if (((MSHR *)(pkt->senderState))->originalCmd == MemCmd::HardPFReq) { DPRINTF(HWPrefetch, "Marking a hardware prefetch as such in the state\n"); return BlkHWPrefetched | BlkValid | BlkWritable; } diff --git a/src/mem/cache/miss/SConscript b/src/mem/cache/miss/SConscript new file mode 100644 index 000000000..0f81a2570 --- /dev/null +++ b/src/mem/cache/miss/SConscript @@ -0,0 +1,37 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +Source('blocking_buffer.cc') +Source('miss_buffer.cc') +Source('miss_queue.cc') +Source('mshr.cc') +Source('mshr_queue.cc') diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index a1af88341..e8ff26880 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -90,7 +90,7 @@ BlockingBuffer::getPacket() } void -BlockingBuffer::setBusCmd(PacketPtr &pkt, Packet::Command cmd) +BlockingBuffer::setBusCmd(PacketPtr &pkt, MemCmd cmd) { MSHR *mshr = (MSHR*) pkt->senderState; mshr->originalCmd = pkt->cmd; @@ -189,7 +189,7 @@ BlockingBuffer::doWriteback(Addr addr, { // Generate request Request * req = new Request(addr, size, 0); - PacketPtr pkt = new Packet(req, Packet::Writeback, -1); + PacketPtr pkt = new Packet(req, MemCmd::Writeback, -1); pkt->allocate(); if (data) { std::memcpy(pkt->getPtr<uint8_t>(), data, size); diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh index 24386a249..86b24d539 100644 --- a/src/mem/cache/miss/blocking_buffer.hh +++ b/src/mem/cache/miss/blocking_buffer.hh @@ -104,7 +104,7 @@ public: * @param pkt The request to update. * @param cmd The bus command to use. */ - void setBusCmd(PacketPtr &pkt, Packet::Command cmd); + void setBusCmd(PacketPtr &pkt, MemCmd cmd); /** * Restore the original command in case of a bus transmission error. diff --git a/src/mem/cache/miss/miss_buffer.hh b/src/mem/cache/miss/miss_buffer.hh index 3e3080578..9a86db304 100644 --- a/src/mem/cache/miss/miss_buffer.hh +++ b/src/mem/cache/miss/miss_buffer.hh @@ -123,7 +123,7 @@ class MissBuffer * @param pkt The request to update. * @param cmd The bus command to use. */ - virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0; + virtual void setBusCmd(PacketPtr &pkt, MemCmd cmd) = 0; /** * Restore the original command in case of a bus transmission error. diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index 38c5ffa71..24ca9cfa2 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -67,17 +67,12 @@ MissQueue::regStats(const string &name) { MissBuffer::regStats(name); - Request temp_req((Addr) NULL, 4, 0); - Packet::Command temp_cmd = Packet::ReadReq; - Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary - temp_pkt.allocate(); - using namespace Stats; // MSHR hit statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshr_hits[access_idx] .init(maxThreadsPerCPU) @@ -92,20 +87,20 @@ MissQueue::regStats(const string &name) .desc("number of demand (read+write) MSHR hits") .flags(total) ; - demandMshrHits = mshr_hits[Packet::ReadReq] + mshr_hits[Packet::WriteReq]; + demandMshrHits = mshr_hits[MemCmd::ReadReq] + mshr_hits[MemCmd::WriteReq]; overallMshrHits .name(name + ".overall_mshr_hits") .desc("number of overall MSHR hits") .flags(total) ; - overallMshrHits = demandMshrHits + mshr_hits[Packet::SoftPFReq] + - mshr_hits[Packet::HardPFReq]; + overallMshrHits = demandMshrHits + mshr_hits[MemCmd::SoftPFReq] + + mshr_hits[MemCmd::HardPFReq]; // MSHR miss statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshr_misses[access_idx] .init(maxThreadsPerCPU) @@ -120,20 +115,20 @@ MissQueue::regStats(const string &name) .desc("number of demand (read+write) MSHR misses") .flags(total) ; - demandMshrMisses = mshr_misses[Packet::ReadReq] + mshr_misses[Packet::WriteReq]; + demandMshrMisses = mshr_misses[MemCmd::ReadReq] + mshr_misses[MemCmd::WriteReq]; overallMshrMisses .name(name + ".overall_mshr_misses") .desc("number of overall MSHR misses") .flags(total) ; - overallMshrMisses = demandMshrMisses + mshr_misses[Packet::SoftPFReq] + - mshr_misses[Packet::HardPFReq]; + overallMshrMisses = demandMshrMisses + mshr_misses[MemCmd::SoftPFReq] + + mshr_misses[MemCmd::HardPFReq]; // MSHR miss latency statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshr_miss_latency[access_idx] .init(maxThreadsPerCPU) @@ -148,8 +143,8 @@ MissQueue::regStats(const string &name) .desc("number of demand (read+write) MSHR miss cycles") .flags(total) ; - demandMshrMissLatency = mshr_miss_latency[Packet::ReadReq] - + mshr_miss_latency[Packet::WriteReq]; + demandMshrMissLatency = mshr_miss_latency[MemCmd::ReadReq] + + mshr_miss_latency[MemCmd::WriteReq]; overallMshrMissLatency .name(name + ".overall_mshr_miss_latency") @@ -157,12 +152,12 @@ MissQueue::regStats(const string &name) .flags(total) ; overallMshrMissLatency = demandMshrMissLatency + - mshr_miss_latency[Packet::SoftPFReq] + mshr_miss_latency[Packet::HardPFReq]; + mshr_miss_latency[MemCmd::SoftPFReq] + mshr_miss_latency[MemCmd::HardPFReq]; // MSHR uncacheable statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshr_uncacheable[access_idx] .init(maxThreadsPerCPU) @@ -177,14 +172,14 @@ MissQueue::regStats(const string &name) .desc("number of overall MSHR uncacheable misses") .flags(total) ; - overallMshrUncacheable = mshr_uncacheable[Packet::ReadReq] - + mshr_uncacheable[Packet::WriteReq] + mshr_uncacheable[Packet::SoftPFReq] - + mshr_uncacheable[Packet::HardPFReq]; + overallMshrUncacheable = mshr_uncacheable[MemCmd::ReadReq] + + mshr_uncacheable[MemCmd::WriteReq] + mshr_uncacheable[MemCmd::SoftPFReq] + + mshr_uncacheable[MemCmd::HardPFReq]; // MSHR miss latency statistics - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshr_uncacheable_lat[access_idx] .init(maxThreadsPerCPU) @@ -199,16 +194,16 @@ MissQueue::regStats(const string &name) .desc("number of overall MSHR uncacheable cycles") .flags(total) ; - overallMshrUncacheableLatency = mshr_uncacheable_lat[Packet::ReadReq] - + mshr_uncacheable_lat[Packet::WriteReq] - + mshr_uncacheable_lat[Packet::SoftPFReq] - + mshr_uncacheable_lat[Packet::HardPFReq]; + overallMshrUncacheableLatency = mshr_uncacheable_lat[MemCmd::ReadReq] + + mshr_uncacheable_lat[MemCmd::WriteReq] + + mshr_uncacheable_lat[MemCmd::SoftPFReq] + + mshr_uncacheable_lat[MemCmd::HardPFReq]; #if 0 // MSHR access formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshrAccesses[access_idx] .name(name + "." + cstr + "_mshr_accesses") @@ -237,9 +232,9 @@ MissQueue::regStats(const string &name) #endif // MSHR miss rate formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); mshrMissRate[access_idx] .name(name + "." + cstr + "_mshr_miss_rate") @@ -266,9 +261,9 @@ MissQueue::regStats(const string &name) overallMshrMissRate = overallMshrMisses / cache->overallAccesses; // mshrMiss latency formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); avgMshrMissLatency[access_idx] .name(name + "." + cstr + "_avg_mshr_miss_latency") @@ -295,9 +290,9 @@ MissQueue::regStats(const string &name) overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; // mshrUncacheable latency formulas - for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { - Packet::Command cmd = (Packet::Command)access_idx; - const string &cstr = temp_pkt.cmdIdxToString(cmd); + for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { + MemCmd cmd(access_idx); + const string &cstr = cmd.toString(); avgMshrUncacheableLatency[access_idx] .name(name + "." + cstr + "_avg_mshr_uncacheable_latency") @@ -351,7 +346,7 @@ MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time) if (mq.isFull()) { cache->setBlocked(Blocked_NoMSHRs); } - if (pkt->cmd != Packet::HardPFReq) { + if (pkt->cmd != MemCmd::HardPFReq) { //If we need to request the bus (not on HW prefetch), do so cache->setMasterRequest(Request_MSHR, time); } @@ -500,17 +495,17 @@ MissQueue::getPacket() } void -MissQueue::setBusCmd(PacketPtr &pkt, Packet::Command cmd) +MissQueue::setBusCmd(PacketPtr &pkt, MemCmd cmd) { assert(pkt->senderState != 0); MSHR * mshr = (MSHR*)pkt->senderState; mshr->originalCmd = pkt->cmd; - if (cmd == Packet::UpgradeReq || cmd == Packet::InvalidateReq) { + if (cmd == MemCmd::UpgradeReq || cmd == MemCmd::InvalidateReq) { pkt->flags |= NO_ALLOCATE; pkt->flags &= ~CACHE_LINE_FILL; } else if (!pkt->req->isUncacheable() && !pkt->isNoAllocate() && - (cmd & (1 << 6)/*NeedsResponse*/)) { + cmd.needsResponse()) { pkt->flags |= CACHE_LINE_FILL; } if (pkt->isCacheFill() || pkt->isNoAllocate()) @@ -552,7 +547,7 @@ MissQueue::markInService(PacketPtr &pkt, MSHR* mshr) if (!mq.havePending()){ cache->clearMasterRequest(Request_MSHR); } - if (mshr->originalCmd == Packet::HardPFReq) { + if (mshr->originalCmd == MemCmd::HardPFReq) { DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n", cache->name()); //Also clear pending if need be @@ -576,7 +571,7 @@ void MissQueue::handleResponse(PacketPtr &pkt, Tick time) { MSHR* mshr = (MSHR*)pkt->senderState; - if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) { + if (((MSHR*)(pkt->senderState))->originalCmd == MemCmd::HardPFReq) { DPRINTF(HWPrefetch, "%s:Handling the response to a HW_PF\n", cache->name()); } @@ -589,7 +584,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time) BlockedCause cause = NUM_BLOCKED_CAUSES; if (pkt->isCacheFill() && !pkt->isNoAllocate()) { - mshr_miss_latency[mshr->originalCmd][0/*pkt->req->getThreadNum()*/] += + mshr_miss_latency[mshr->originalCmd.toInt()][0/*pkt->req->getThreadNum()*/] += curTick - pkt->time; // targets were handled in the cache tags if (mshr == noTargetMSHR) { @@ -601,7 +596,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time) if (mshr->hasTargets()) { // Didn't satisfy all the targets, need to resend - Packet::Command cmd = mshr->getTarget()->cmd; + MemCmd cmd = mshr->getTarget()->cmd; mshr->pkt->setDest(Packet::Broadcast); mshr->pkt->result = Packet::Unknown; mshr->pkt->req = mshr->getTarget()->req; @@ -619,7 +614,7 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time) } } else { if (pkt->req->isUncacheable()) { - mshr_uncacheable_lat[pkt->cmd][0/*pkt->req->getThreadNum()*/] += + mshr_uncacheable_lat[pkt->cmd.toInt()][0/*pkt->req->getThreadNum()*/] += curTick - pkt->time; } if (mshr->hasTargets() && pkt->req->isUncacheable()) { @@ -714,7 +709,7 @@ MissQueue::doWriteback(Addr addr, { // Generate request Request * req = new Request(addr, size, 0); - PacketPtr pkt = new Packet(req, Packet::Writeback, -1); + PacketPtr pkt = new Packet(req, MemCmd::Writeback, -1); pkt->allocate(); if (data) { memcpy(pkt->getPtr<uint8_t>(), data, size); diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh index 1f9bb1e0c..d3560ff36 100644 --- a/src/mem/cache/miss/miss_queue.hh +++ b/src/mem/cache/miss/miss_queue.hh @@ -77,59 +77,59 @@ class MissQueue : public MissBuffer * @{ */ /** Number of misses that hit in the MSHRs per command and thread. */ - Stats::Vector<> mshr_hits[NUM_MEM_CMDS]; + Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS]; /** Demand misses that hit in the MSHRs. */ Stats::Formula demandMshrHits; /** Total number of misses that hit in the MSHRs. */ Stats::Formula overallMshrHits; /** Number of misses that miss in the MSHRs, per command and thread. */ - Stats::Vector<> mshr_misses[NUM_MEM_CMDS]; + Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS]; /** Demand misses that miss in the MSHRs. */ Stats::Formula demandMshrMisses; /** Total number of misses that miss in the MSHRs. */ Stats::Formula overallMshrMisses; /** Number of misses that miss in the MSHRs, per command and thread. */ - Stats::Vector<> mshr_uncacheable[NUM_MEM_CMDS]; + Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; /** Total number of misses that miss in the MSHRs. */ Stats::Formula overallMshrUncacheable; /** Total cycle latency of each MSHR miss, per command and thread. */ - Stats::Vector<> mshr_miss_latency[NUM_MEM_CMDS]; + Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; /** Total cycle latency of demand MSHR misses. */ Stats::Formula demandMshrMissLatency; /** Total cycle latency of overall MSHR misses. */ Stats::Formula overallMshrMissLatency; /** Total cycle latency of each MSHR miss, per command and thread. */ - Stats::Vector<> mshr_uncacheable_lat[NUM_MEM_CMDS]; + Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; /** Total cycle latency of overall MSHR misses. */ Stats::Formula overallMshrUncacheableLatency; /** The total number of MSHR accesses per command and thread. */ - Stats::Formula mshrAccesses[NUM_MEM_CMDS]; + Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; /** The total number of demand MSHR accesses. */ Stats::Formula demandMshrAccesses; /** The total number of MSHR accesses. */ Stats::Formula overallMshrAccesses; /** The miss rate in the MSHRs pre command and thread. */ - Stats::Formula mshrMissRate[NUM_MEM_CMDS]; + Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; /** The demand miss rate in the MSHRs. */ Stats::Formula demandMshrMissRate; /** The overall miss rate in the MSHRs. */ Stats::Formula overallMshrMissRate; /** The average latency of an MSHR miss, per command and thread. */ - Stats::Formula avgMshrMissLatency[NUM_MEM_CMDS]; + Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; /** The average latency of a demand MSHR miss. */ Stats::Formula demandAvgMshrMissLatency; /** The average overall latency of an MSHR miss. */ Stats::Formula overallAvgMshrMissLatency; /** The average latency of an MSHR miss, per command and thread. */ - Stats::Formula avgMshrUncacheableLatency[NUM_MEM_CMDS]; + Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; /** The average overall latency of an MSHR miss. */ Stats::Formula overallAvgMshrUncacheableLatency; @@ -220,7 +220,7 @@ class MissQueue : public MissBuffer * @param pkt The request to update. * @param cmd The bus command to use. */ - void setBusCmd(PacketPtr &pkt, Packet::Command cmd); + void setBusCmd(PacketPtr &pkt, MemCmd cmd); /** * Restore the original command in case of a bus transmission error. diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index fc520b4b4..74dad658b 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -39,7 +39,7 @@ #include <vector> #include "mem/cache/miss/mshr.hh" -#include "sim/root.hh" // for curTick +#include "sim/core.hh" // for curTick #include "sim/host.hh" #include "base/misc.hh" #include "mem/cache/cache.hh" @@ -54,7 +54,7 @@ MSHR::MSHR() } void -MSHR::allocate(Packet::Command cmd, Addr _addr, int size, +MSHR::allocate(MemCmd cmd, Addr _addr, int size, PacketPtr &target) { addr = _addr; @@ -148,7 +148,7 @@ MSHR::allocateTarget(PacketPtr &target) */ if (!inService && target->isWrite()) { - pkt->cmd = Packet::WriteReq; + pkt->cmd = MemCmd::WriteReq; } } diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh index 281ea9d49..d0410acda 100644 --- a/src/mem/cache/miss/mshr.hh +++ b/src/mem/cache/miss/mshr.hh @@ -72,7 +72,7 @@ class MSHR { /** The number of currently allocated targets. */ short ntargets; /** The original requesting command. */ - Packet::Command originalCmd; + MemCmd originalCmd; /** Order number of assigned by the miss queue. */ uint64_t order; @@ -100,7 +100,7 @@ public: * @param size The number of bytes to request. * @param pkt The original miss. */ - void allocate(Packet::Command cmd, Addr addr, int size, + void allocate(MemCmd cmd, Addr addr, int size, PacketPtr &pkt); /** diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 6cb62429d..add11dfe7 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -136,7 +136,7 @@ MSHRQueue::allocateFetch(Addr addr, int size, PacketPtr &target) MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); - mshr->allocate(Packet::ReadReq, addr, size, target); + mshr->allocate(MemCmd::ReadReq, addr, size, target); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->readyIter = pendingList.insert(pendingList.end(), mshr); @@ -151,7 +151,7 @@ MSHRQueue::allocateTargetList(Addr addr, int size) assert(mshr->getNumTargets() == 0); freeList.pop_front(); PacketPtr dummy; - mshr->allocate(Packet::ReadReq, addr, size, dummy); + mshr->allocate(MemCmd::ReadReq, addr, size, dummy); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->inService = true; ++inServiceMSHRs; @@ -196,7 +196,7 @@ void MSHRQueue::markInService(MSHR* mshr) { //assert(mshr == pendingList.front()); - if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) { + if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == MemCmd::UpgradeReq)) { assert(mshr->getNumTargets() == 0); deallocate(mshr); return; @@ -209,7 +209,7 @@ MSHRQueue::markInService(MSHR* mshr) } void -MSHRQueue::markPending(MSHR* mshr, Packet::Command cmd) +MSHRQueue::markPending(MSHR* mshr, MemCmd cmd) { //assert(mshr->readyIter == NULL); mshr->pkt->cmd = cmd; diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh index ec2ddae8a..5069db661 100644 --- a/src/mem/cache/miss/mshr_queue.hh +++ b/src/mem/cache/miss/mshr_queue.hh @@ -185,7 +185,7 @@ class MSHRQueue { * @param mshr The MSHR to resend. * @param cmd The command to resend. */ - void markPending(MSHR* mshr, Packet::Command cmd); + void markPending(MSHR* mshr, MemCmd cmd); /** * Squash outstanding requests with the given thread number. If a request diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript new file mode 100644 index 000000000..8a7f1232c --- /dev/null +++ b/src/mem/cache/prefetch/SConscript @@ -0,0 +1,37 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +Source('base_prefetcher.cc') +Source('ghb_prefetcher.cc') +Source('stride_prefetcher.cc') +Source('tagged_prefetcher.cc') + diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc index 4254800b1..44daf75e1 100644 --- a/src/mem/cache/prefetch/base_prefetcher.cc +++ b/src/mem/cache/prefetch/base_prefetcher.cc @@ -200,7 +200,7 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time) //create a prefetch memreq Request * prefetchReq = new Request(*addr, blkSize, 0); PacketPtr prefetch; - prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1); + prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, -1); prefetch->allocate(); prefetch->req->setThreadContext(pkt->req->getCpuNum(), pkt->req->getThreadNum()); diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript new file mode 100644 index 000000000..baf71f687 --- /dev/null +++ b/src/mem/cache/tags/SConscript @@ -0,0 +1,42 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +Source('base_tags.cc') +Source('fa_lru.cc') +Source('iic.cc') +Source('lru.cc') +Source('split.cc') +Source('split_lifo.cc') +Source('split_lru.cc') + +Source('repl/gen.cc') +Source('repl/repl.cc') diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index e547e112e..9c802d0dc 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -42,7 +42,7 @@ #include "mem/cache/base_cache.hh" #include "mem/cache/tags/iic.hh" #include "base/intmath.hh" -#include "sim/root.hh" // for curTick +#include "sim/core.hh" // for curTick #include "base/trace.hh" // for DPRINTF @@ -372,7 +372,8 @@ IIC::freeReplacementBlock(PacketList & writebacks) */ Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0), blkSize, 0); - PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1); + PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, + -1); writeback->allocate(); memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize); diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 102bb3506..8e8779774 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -38,7 +38,7 @@ #include "mem/cache/base_cache.hh" #include "base/intmath.hh" #include "mem/cache/tags/lru.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc index 792ff8fa7..d71d1a3ef 100644 --- a/src/mem/cache/tags/split_lifo.cc +++ b/src/mem/cache/tags/split_lifo.cc @@ -38,7 +38,7 @@ #include "mem/cache/base_cache.hh" #include "base/intmath.hh" #include "mem/cache/tags/split_lifo.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "base/trace.hh" using namespace std; diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc index c37d72cb7..7227fb5c1 100644 --- a/src/mem/cache/tags/split_lru.cc +++ b/src/mem/cache/tags/split_lru.cc @@ -38,7 +38,7 @@ #include "mem/cache/base_cache.hh" #include "base/intmath.hh" #include "mem/cache/tags/split_lru.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc index d4d3fd283..ef31cf999 100644 --- a/src/mem/mem_object.cc +++ b/src/mem/mem_object.cc @@ -35,5 +35,10 @@ MemObject::MemObject(const std::string &name) : SimObject(name) { } +void +MemObject::deletePortRefs(Port *p) +{ + panic("This object does not support port deletion\n"); +} DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject) diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh index d12eeffe0..ec6fa2b2a 100644 --- a/src/mem/mem_object.hh +++ b/src/mem/mem_object.hh @@ -51,6 +51,10 @@ class MemObject : public SimObject public: /** Additional function to return the Port of a memory object. */ virtual Port *getPort(const std::string &if_name, int idx = -1) = 0; + + /** Tell object that this port is about to disappear, so it should remove it + * from any structures that it's keeping it in. */ + virtual void deletePortRefs(Port *p) ; }; #endif //__MEM_MEM_OBJECT_HH__ diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 44805236c..14d08db1b 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -41,68 +41,68 @@ #include "base/trace.hh" #include "mem/packet.hh" -static const std::string ReadReqString("ReadReq"); -static const std::string WriteReqString("WriteReq"); -static const std::string WriteReqNoAckString("WriteReqNoAck|Writeback"); -static const std::string ReadRespString("ReadResp"); -static const std::string WriteRespString("WriteResp"); -static const std::string SoftPFReqString("SoftPFReq"); -static const std::string SoftPFRespString("SoftPFResp"); -static const std::string HardPFReqString("HardPFReq"); -static const std::string HardPFRespString("HardPFResp"); -static const std::string InvalidateReqString("InvalidateReq"); -static const std::string WriteInvalidateReqString("WriteInvalidateReq"); -static const std::string WriteInvalidateRespString("WriteInvalidateResp"); -static const std::string UpgradeReqString("UpgradeReq"); -static const std::string ReadExReqString("ReadExReq"); -static const std::string ReadExRespString("ReadExResp"); -static const std::string OtherCmdString("<other>"); +// The one downside to bitsets is that static initializers can get ugly. +#define SET1(a1) (1 << (a1)) +#define SET2(a1, a2) (SET1(a1) | SET1(a2)) +#define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3)) +#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4)) +#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5)) +#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6)) -const std::string & -Packet::cmdString() const +const MemCmd::CommandInfo +MemCmd::commandInfo[] = { - switch (cmd) { - case ReadReq: return ReadReqString; - case WriteReq: return WriteReqString; - case WriteReqNoAck: return WriteReqNoAckString; - case ReadResp: return ReadRespString; - case WriteResp: return WriteRespString; - case SoftPFReq: return SoftPFReqString; - case SoftPFResp: return SoftPFRespString; - case HardPFReq: return HardPFReqString; - case HardPFResp: return HardPFRespString; - case InvalidateReq: return InvalidateReqString; - case WriteInvalidateReq:return WriteInvalidateReqString; - case WriteInvalidateResp:return WriteInvalidateRespString; - case UpgradeReq: return UpgradeReqString; - case ReadExReq: return ReadExReqString; - case ReadExResp: return ReadExRespString; - default: return OtherCmdString; - } -} + /* InvalidCmd */ + { 0, InvalidCmd, "InvalidCmd" }, + /* ReadReq */ + { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" }, + /* WriteReq */ + { SET4(IsWrite, IsRequest, NeedsResponse, HasData), + WriteResp, "WriteReq" }, + /* WriteReqNoAck */ + { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "WriteReqNoAck" }, + /* ReadResp */ + { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" }, + /* WriteResp */ + { SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" }, + /* Writeback */ + { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "Writeback" }, + /* SoftPFReq */ + { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), + SoftPFResp, "SoftPFReq" }, + /* HardPFReq */ + { SET4(IsRead, IsRequest, IsHWPrefetch, NeedsResponse), + HardPFResp, "HardPFReq" }, + /* SoftPFResp */ + { SET4(IsRead, IsResponse, IsSWPrefetch, HasData), + InvalidCmd, "SoftPFResp" }, + /* HardPFResp */ + { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), + InvalidCmd, "HardPFResp" }, + /* InvalidateReq */ + { SET2(IsInvalidate, IsRequest), InvalidCmd, "InvalidateReq" }, + /* WriteInvalidateReq */ + { SET5(IsWrite, IsInvalidate, IsRequest, HasData, NeedsResponse), + WriteInvalidateResp, "WriteInvalidateReq" }, + /* WriteInvalidateResp */ + { SET5(IsWrite, IsInvalidate, IsRequest, NeedsResponse, IsResponse), + InvalidCmd, "WriteInvalidateResp" }, + /* UpgradeReq */ + { SET3(IsInvalidate, IsRequest, IsUpgrade), InvalidCmd, "UpgradeReq" }, + /* ReadExReq */ + { SET4(IsRead, IsInvalidate, IsRequest, NeedsResponse), + ReadExResp, "ReadExReq" }, + /* ReadExResp */ + { SET4(IsRead, IsInvalidate, IsResponse, HasData), + InvalidCmd, "ReadExResp" }, + /* SwapReq -- for Swap ldstub type operations */ + { SET4(IsReadWrite, IsRequest, HasData, NeedsResponse), + SwapResp, "SwapReq" }, + /* SwapResp -- for Swap ldstub type operations */ + { SET3(IsReadWrite, IsResponse, HasData), + InvalidCmd, "SwapResp" } +}; -const std::string & -Packet::cmdIdxToString(Packet::Command idx) -{ - switch (idx) { - case ReadReq: return ReadReqString; - case WriteReq: return WriteReqString; - case WriteReqNoAck: return WriteReqNoAckString; - case ReadResp: return ReadRespString; - case WriteResp: return WriteRespString; - case SoftPFReq: return SoftPFReqString; - case SoftPFResp: return SoftPFRespString; - case HardPFReq: return HardPFReqString; - case HardPFResp: return HardPFRespString; - case InvalidateReq: return InvalidateReqString; - case WriteInvalidateReq:return WriteInvalidateReqString; - case WriteInvalidateResp:return WriteInvalidateRespString; - case UpgradeReq: return UpgradeReqString; - case ReadExReq: return ReadExReqString; - case ReadExResp: return ReadExRespString; - default: return OtherCmdString; - } -} /** delete the data pointed to in the data pointer. Ok to call to matter how * data was allocted. */ @@ -149,9 +149,17 @@ fixDelayedResponsePacket(PacketPtr func, PacketPtr timing) bool result; if (timing->isRead() || timing->isWrite()) { - timing->toggleData(); + // Ugly hack to deal with the fact that we queue the requests + // and don't convert them to responses until we issue them on + // the bus. I tried to avoid this by converting packets to + // responses right away, but this breaks during snoops where a + // responder may do the conversion before other caches have + // done the snoop. Would work if we copied the packet instead + // of just hanging on to a pointer. + MemCmd oldCmd = timing->cmd; + timing->cmd = timing->cmd.responseCommand(); result = fixPacket(func, timing); - timing->toggleData(); + timing->cmd = oldCmd; } else { //Don't toggle if it isn't a read/write response @@ -171,11 +179,6 @@ fixPacket(PacketPtr func, PacketPtr timing) assert(!(funcStart > timingEnd || timingStart > funcEnd)); - if (DTRACE(FunctionalAccess)) { - DebugOut() << func; - DebugOut() << timing; - } - // this packet can't solve our problem, continue on if (!timing->hasData()) return true; @@ -241,9 +244,11 @@ operator<<(std::ostream &o, const Packet &p) if (p.isRead()) o << "Read "; if (p.isWrite()) - o << "Read "; + o << "Write "; + if (p.isReadWrite()) + o << "Read/Write "; if (p.isInvalidate()) - o << "Read "; + o << "Invalidate "; if (p.isRequest()) o << "Request "; if (p.isResponse()) diff --git a/src/mem/packet.hh b/src/mem/packet.hh index a4c003e8b..dc23e9f6d 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -40,12 +40,13 @@ #include <cassert> #include <list> +#include <bitset> #include "base/compiler.hh" #include "base/misc.hh" #include "mem/request.hh" #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" struct Packet; @@ -62,8 +63,118 @@ typedef std::list<PacketPtr> PacketList; #define NO_ALLOCATE (1 << 5) #define SNOOP_COMMIT (1 << 6) -//for now. @todo fix later -#define NUM_MEM_CMDS (1 << 11) + +class MemCmd +{ + public: + + /** List of all commands associated with a packet. */ + enum Command + { + InvalidCmd, + ReadReq, + WriteReq, + WriteReqNoAck, + ReadResp, + WriteResp, + Writeback, + SoftPFReq, + HardPFReq, + SoftPFResp, + HardPFResp, + InvalidateReq, + WriteInvalidateReq, + WriteInvalidateResp, + UpgradeReq, + ReadExReq, + ReadExResp, + SwapReq, + SwapResp, + NUM_MEM_CMDS + }; + + private: + /** List of command attributes. */ + enum Attribute + { + IsRead, + IsWrite, + IsPrefetch, + IsInvalidate, + IsRequest, + IsResponse, + NeedsResponse, + IsSWPrefetch, + IsHWPrefetch, + IsUpgrade, + HasData, + IsReadWrite, + NUM_COMMAND_ATTRIBUTES + }; + + /** Structure that defines attributes and other data associated + * with a Command. */ + struct CommandInfo { + /** Set of attribute flags. */ + const std::bitset<NUM_COMMAND_ATTRIBUTES> attributes; + /** Corresponding response for requests; InvalidCmd if no + * response is applicable. */ + const Command response; + /** String representation (for printing) */ + const std::string str; + }; + + /** Array to map Command enum to associated info. */ + static const CommandInfo commandInfo[]; + + private: + + Command cmd; + + bool testCmdAttrib(MemCmd::Attribute attrib) const { + return commandInfo[cmd].attributes[attrib] != 0; + } + + public: + + bool isRead() const { return testCmdAttrib(IsRead); } + bool isWrite() const { return testCmdAttrib(IsWrite); } + bool isRequest() const { return testCmdAttrib(IsRequest); } + bool isResponse() const { return testCmdAttrib(IsResponse); } + bool needsResponse() const { return testCmdAttrib(NeedsResponse); } + bool isInvalidate() const { return testCmdAttrib(IsInvalidate); } + bool hasData() const { return testCmdAttrib(HasData); } + bool isReadWrite() const { return testCmdAttrib(IsReadWrite); } + + const Command responseCommand() const { + return commandInfo[cmd].response; + } + + /** Return the string to a cmd given by idx. */ + const std::string &toString() const { + return commandInfo[cmd].str; + } + + int toInt() const { return (int)cmd; } + + MemCmd(Command _cmd) + : cmd(_cmd) + { } + + MemCmd(int _cmd) + : cmd((Command)_cmd) + { } + + MemCmd() + : cmd(InvalidCmd) + { } + + bool operator==(MemCmd c2) { return (cmd == c2.cmd); } + bool operator!=(MemCmd c2) { return (cmd != c2.cmd); } + + friend class Packet; +}; + /** * A Packet is used to encapsulate a transfer between two objects in * the memory system (e.g., the L1 and L2 cache). (In contrast, a @@ -74,6 +185,9 @@ typedef std::list<PacketPtr> PacketList; class Packet { public: + + typedef MemCmd::Command Command; + /** Temporary FLAGS field until cache gets working, this should be in coherence/sender state. */ uint64_t flags; @@ -169,73 +283,28 @@ class Packet * to cast to the state appropriate to the sender. */ SenderState *senderState; - private: - /** List of command attributes. */ - // If you add a new CommandAttribute, make sure to increase NUM_MEM_CMDS - // as well. - enum CommandAttribute - { - IsRead = 1 << 0, - IsWrite = 1 << 1, - IsPrefetch = 1 << 2, - IsInvalidate = 1 << 3, - IsRequest = 1 << 4, - IsResponse = 1 << 5, - NeedsResponse = 1 << 6, - IsSWPrefetch = 1 << 7, - IsHWPrefetch = 1 << 8, - IsUpgrade = 1 << 9, - HasData = 1 << 10 - }; - public: - /** List of all commands associated with a packet. */ - enum Command - { - InvalidCmd = 0, - ReadReq = IsRead | IsRequest | NeedsResponse, - WriteReq = IsWrite | IsRequest | NeedsResponse | HasData, - WriteReqNoAck = IsWrite | IsRequest | HasData, - ReadResp = IsRead | IsResponse | NeedsResponse | HasData, - WriteResp = IsWrite | IsResponse | NeedsResponse, - Writeback = IsWrite | IsRequest | HasData, - SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse, - HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse, - SoftPFResp = IsRead | IsResponse | IsSWPrefetch - | NeedsResponse | HasData, - HardPFResp = IsRead | IsResponse | IsHWPrefetch - | NeedsResponse | HasData, - InvalidateReq = IsInvalidate | IsRequest, - WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest - | HasData | NeedsResponse, - WriteInvalidateResp = IsWrite | IsInvalidate | IsRequest - | NeedsResponse | IsResponse, - UpgradeReq = IsInvalidate | IsRequest | IsUpgrade, - ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse, - ReadExResp = IsRead | IsInvalidate | IsResponse - | NeedsResponse | HasData - }; + + /** The command field of the packet. */ + MemCmd cmd; /** Return the string name of the cmd field (for debugging and * tracing). */ - const std::string &cmdString() const; - - /** Reutrn the string to a cmd given by idx. */ - const std::string &cmdIdxToString(Command idx); + const std::string &cmdString() const { return cmd.toString(); } /** Return the index of this command. */ - inline int cmdToIndex() const { return (int) cmd; } + inline int cmdToIndex() const { return cmd.toInt(); } - /** The command field of the packet. */ - Command cmd; + public: - bool isRead() const { return (cmd & IsRead) != 0; } - bool isWrite() const { return (cmd & IsWrite) != 0; } - bool isRequest() const { return (cmd & IsRequest) != 0; } - bool isResponse() const { return (cmd & IsResponse) != 0; } - bool needsResponse() const { return (cmd & NeedsResponse) != 0; } - bool isInvalidate() const { return (cmd & IsInvalidate) != 0; } - bool hasData() const { return (cmd & HasData) != 0; } + bool isRead() const { return cmd.isRead(); } + bool isWrite() const { return cmd.isWrite(); } + bool isRequest() const { return cmd.isRequest(); } + bool isResponse() const { return cmd.isResponse(); } + bool needsResponse() const { return cmd.needsResponse(); } + bool isInvalidate() const { return cmd.isInvalidate(); } + bool hasData() const { return cmd.hasData(); } + bool isReadWrite() const { return cmd.isReadWrite(); } bool isCacheFill() const { return (flags & CACHE_LINE_FILL) != 0; } bool isNoAllocate() const { return (flags & NO_ALLOCATE) != 0; } @@ -269,13 +338,13 @@ class Packet Addr getOffset(int blkSize) const { return addr & (Addr)(blkSize - 1); } void addrOverride(Addr newAddr) { assert(addrSizeValid); addr = newAddr; } - void cmdOverride(Command newCmd) { cmd = newCmd; } + void cmdOverride(MemCmd newCmd) { cmd = newCmd; } /** Constructor. Note that a Request object must be constructed * first, but the Requests's physical address and size fields * need not be valid. The command and destination addresses * must be supplied. */ - Packet(Request *_req, Command _cmd, short _dest) + Packet(Request *_req, MemCmd _cmd, short _dest) : data(NULL), staticData(false), dynamicData(false), arrayData(false), addr(_req->paddr), size(_req->size), dest(_dest), addrSizeValid(_req->validPaddr), @@ -290,7 +359,7 @@ class Packet /** Alternate constructor if you are trying to create a packet with * a request that is for a whole block, not the address from the req. * this allows for overriding the size/addr of the req.*/ - Packet(Request *_req, Command _cmd, short _dest, int _blkSize) + Packet(Request *_req, MemCmd _cmd, short _dest, int _blkSize) : data(NULL), staticData(false), dynamicData(false), arrayData(false), addr(_req->paddr & ~(_blkSize - 1)), size(_blkSize), dest(_dest), @@ -335,25 +404,11 @@ class Packet void makeTimingResponse() { assert(needsResponse()); assert(isRequest()); - int icmd = (int)cmd; - icmd &= ~(IsRequest); - icmd |= IsResponse; - if (isRead()) - icmd |= HasData; - if (isWrite()) - icmd &= ~HasData; - cmd = (Command)icmd; + cmd = cmd.responseCommand(); dest = src; srcValid = false; } - - void toggleData() { - int icmd = (int)cmd; - icmd ^= HasData; - cmd = (Command)icmd; - } - /** * Take a request packet and modify it in place to be suitable for * returning as a response to that request. @@ -362,14 +417,7 @@ class Packet { assert(needsResponse()); assert(isRequest()); - int icmd = (int)cmd; - icmd &= ~(IsRequest); - icmd |= IsResponse; - if (isRead()) - icmd |= HasData; - if (isWrite()) - icmd &= ~HasData; - cmd = (Command)icmd; + cmd = cmd.responseCommand(); } /** diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh index aac0c3ae5..d1edd00aa 100644 --- a/src/mem/packet_access.hh +++ b/src/mem/packet_access.hh @@ -30,6 +30,7 @@ */ #include "arch/isa_traits.hh" +#include "base/bigint.hh" #include "mem/packet.hh" #include "sim/byteswap.hh" diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index fe8094b88..96bc23793 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -157,7 +157,7 @@ PageTable::translate(RequestPtr &req) assert(pageAlign(req->getVaddr() + req->getSize() - 1) == pageAlign(req->getVaddr())); if (!translate(req->getVaddr(), paddr)) { - return genPageTableFault(req->getVaddr()); + return Fault(new PageTableFault(req->getVaddr())); } req->setPaddr(paddr); return page_check(req->getPaddr(), req->getSize()); diff --git a/src/mem/physical.cc b/src/mem/physical.cc index eccd42bec..5d7d7382a 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -92,7 +92,7 @@ Addr PhysicalMemory::new_page() { Addr return_addr = pagePtr << LogVMPageSize; - return_addr += params()->addrRange.start; + return_addr += start(); ++pagePtr; return return_addr; @@ -187,7 +187,7 @@ PhysicalMemory::checkLockedAddrList(Request *req) } if (isLocked) { - req->setScResult(success ? 1 : 0); + req->setExtraData(success ? 1 : 0); } return success; @@ -196,16 +196,14 @@ PhysicalMemory::checkLockedAddrList(Request *req) void PhysicalMemory::doFunctionalAccess(PacketPtr pkt) { - assert(pkt->getAddr() >= params()->addrRange.start && - pkt->getAddr() + pkt->getSize() <= params()->addrRange.start + - params()->addrRange.size()); + assert(pkt->getAddr() >= start() && + pkt->getAddr() + pkt->getSize() <= start() + size()); if (pkt->isRead()) { if (pkt->req->isLocked()) { trackLoadLocked(pkt->req); } - memcpy(pkt->getPtr<uint8_t>(), - pmemAddr + pkt->getAddr() - params()->addrRange.start, + memcpy(pkt->getPtr<uint8_t>(), pmemAddr + pkt->getAddr() - start(), pkt->getSize()); #if TRACING_ON switch (pkt->getSize()) { @@ -233,8 +231,8 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt) } else if (pkt->isWrite()) { if (writeOK(pkt->req)) { - memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start, - pkt->getPtr<uint8_t>(), pkt->getSize()); + memcpy(pmemAddr + pkt->getAddr() - start(), pkt->getPtr<uint8_t>(), + pkt->getSize()); #if TRACING_ON switch (pkt->getSize()) { case sizeof(uint64_t): @@ -259,12 +257,75 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt) } #endif } - } - else if (pkt->isInvalidate()) { + } else if (pkt->isInvalidate()) { //upgrade or invalidate pkt->flags |= SATISFIED; - } - else { + } else if (pkt->isReadWrite()) { + IntReg overwrite_val; + bool overwrite_mem; + uint64_t condition_val64; + uint32_t condition_val32; + + assert(sizeof(IntReg) >= pkt->getSize()); + + overwrite_mem = true; + // keep a copy of our possible write value, and copy what is at the + // memory address into the packet + std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize()); + std::memcpy(pkt->getPtr<uint8_t>(), pmemAddr + pkt->getAddr() - start(), + pkt->getSize()); + + if (pkt->req->isCondSwap()) { + if (pkt->getSize() == sizeof(uint64_t)) { + condition_val64 = pkt->req->getExtraData(); + overwrite_mem = !std::memcmp(&condition_val64, pmemAddr + + pkt->getAddr() - start(), sizeof(uint64_t)); + } else if (pkt->getSize() == sizeof(uint32_t)) { + condition_val32 = (uint32_t)pkt->req->getExtraData(); + overwrite_mem = !std::memcmp(&condition_val32, pmemAddr + + pkt->getAddr() - start(), sizeof(uint32_t)); + } else + panic("Invalid size for conditional read/write\n"); + } + + if (overwrite_mem) + std::memcpy(pmemAddr + pkt->getAddr() - start(), + &overwrite_val, pkt->getSize()); + +#if TRACING_ON + switch (pkt->getSize()) { + case sizeof(uint64_t): + DPRINTF(MemoryAccess, "Read/Write of size %i on address 0x%x old data 0x%x\n", + pkt->getSize(), pkt->getAddr(),pkt->get<uint64_t>()); + DPRINTF(MemoryAccess, "New Data 0x%x %s conditional (0x%x) and %s \n", + overwrite_mem, pkt->req->isCondSwap() ? "was" : "wasn't", + condition_val64, overwrite_mem ? "happened" : "didn't happen"); + break; + case sizeof(uint32_t): + DPRINTF(MemoryAccess, "Read/Write of size %i on address 0x%x old data 0x%x\n", + pkt->getSize(), pkt->getAddr(),pkt->get<uint32_t>()); + DPRINTF(MemoryAccess, "New Data 0x%x %s conditional (0x%x) and %s \n", + overwrite_mem, pkt->req->isCondSwap() ? "was" : "wasn't", + condition_val32, overwrite_mem ? "happened" : "didn't happen"); + break; + case sizeof(uint16_t): + DPRINTF(MemoryAccess, "Read/Write of size %i on address 0x%x old data 0x%x\n", + pkt->getSize(), pkt->getAddr(),pkt->get<uint16_t>()); + DPRINTF(MemoryAccess, "New Data 0x%x wasn't conditional and happned\n", + overwrite_mem); + break; + case sizeof(uint8_t): + DPRINTF(MemoryAccess, "Read/Write of size %i on address 0x%x old data 0x%x\n", + pkt->getSize(), pkt->getAddr(),pkt->get<uint8_t>()); + DPRINTF(MemoryAccess, "New Data 0x%x wasn't conditional and happned\n", + overwrite_mem); + break; + default: + DPRINTF(MemoryAccess, "Read/Write of size %i on address 0x%x\n", + pkt->getSize(), pkt->getAddr()); + } +#endif + } else { panic("unimplemented"); } @@ -315,7 +376,7 @@ PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { snoop.clear(); resp.clear(); - resp.push_back(RangeSize(params()->addrRange.start, + resp.push_back(RangeSize(start(), params()->addrRange.size())); } diff --git a/src/mem/physical.hh b/src/mem/physical.hh index af88bcaa0..f7200b502 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -131,7 +131,7 @@ class PhysicalMemory : public MemObject // no locked addrs: nothing to check, store_conditional fails bool isLocked = req->isLocked(); if (isLocked) { - req->setScResult(0); + req->setExtraData(0); } return !isLocked; // only do write if not an sc } else { @@ -148,6 +148,7 @@ class PhysicalMemory : public MemObject public: Addr new_page(); uint64_t size() { return params()->addrRange.size(); } + uint64_t start() { return params()->addrRange.start; } struct Params { diff --git a/src/mem/port.cc b/src/mem/port.cc index da719bbd9..e75e50e4d 100644 --- a/src/mem/port.cc +++ b/src/mem/port.cc @@ -36,6 +36,7 @@ #include "base/chunk_generator.hh" #include "base/trace.hh" +#include "mem/mem_object.hh" #include "mem/port.hh" void @@ -46,7 +47,16 @@ Port::setPeer(Port *port) } void -Port::blobHelper(Addr addr, uint8_t *p, int size, Packet::Command cmd) +Port::removeConn() +{ + if (peer->getOwner()) + peer->getOwner()->deletePortRefs(peer); + delete peer; + peer = NULL; +} + +void +Port::blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd) { Request req; Packet pkt(&req, cmd, Packet::Broadcast); @@ -64,13 +74,13 @@ Port::blobHelper(Addr addr, uint8_t *p, int size, Packet::Command cmd) void Port::writeBlob(Addr addr, uint8_t *p, int size) { - blobHelper(addr, p, size, Packet::WriteReq); + blobHelper(addr, p, size, MemCmd::WriteReq); } void Port::readBlob(Addr addr, uint8_t *p, int size) { - blobHelper(addr, p, size, Packet::ReadReq); + blobHelper(addr, p, size, MemCmd::ReadReq); } void @@ -80,7 +90,7 @@ Port::memsetBlob(Addr addr, uint8_t val, int size) uint8_t *buf = new uint8_t[size]; std::memset(buf, val, size); - blobHelper(addr, buf, size, Packet::WriteReq); + blobHelper(addr, buf, size, MemCmd::WriteReq); delete [] buf; } diff --git a/src/mem/port.hh b/src/mem/port.hh index 5e55225bf..6296b42ca 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -120,7 +120,7 @@ class Port { portName = name; } /** Function to set the pointer for the peer port. */ - void setPeer(Port *port); + virtual void setPeer(Port *port); /** Function to get the pointer to the peer port. */ Port *getPeer() { return peer; } @@ -131,6 +131,11 @@ class Port /** Function to return the owner of this port. */ MemObject *getOwner() { return owner; } + /** Inform the peer port to delete itself and notify it's owner about it's + * demise. */ + void removeConn(); + + protected: /** These functions are protected because they should only be @@ -245,7 +250,7 @@ class Port /** Internal helper function for read/writeBlob(). */ - void blobHelper(Addr addr, uint8_t *p, int size, Packet::Command cmd); + void blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd); }; /** A simple functional port that is only meant for one way communication to diff --git a/src/mem/request.hh b/src/mem/request.hh index de0512e1c..d2ebc91d3 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -40,7 +40,7 @@ #define __MEM_REQUEST_HH__ #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include <cassert> @@ -71,6 +71,10 @@ const uint32_t EVICT_NEXT = 0x20000; const uint32_t NO_ALIGN_FAULT = 0x40000; /** The request was an instruction read. */ const uint32_t INST_READ = 0x80000; +/** This request is for a memory swap. */ +const uint32_t MEM_SWAP = 0x100000; +const uint32_t MEM_SWAP_COND = 0x200000; + class Request { @@ -104,8 +108,9 @@ class Request /** The virtual address of the request. */ Addr vaddr; - /** The return value of store conditional. */ - uint64_t scResult; + /** Extra data for the request, such as the return value of + * store conditional or the compare value for a CAS. */ + uint64_t extraData; /** The cpu number (for statistics, typically). */ int cpuNum; @@ -120,7 +125,7 @@ class Request /** Whether or not the asid & vaddr are valid. */ bool validAsidVaddr; /** Whether or not the sc result is valid. */ - bool validScResult; + bool validExData; /** Whether or not the cpu number & thread ID are valid. */ bool validCpuAndThreadNums; /** Whether or not the pc is valid. */ @@ -130,7 +135,7 @@ class Request /** Minimal constructor. No fields are initialized. */ Request() : validPaddr(false), validAsidVaddr(false), - validScResult(false), validCpuAndThreadNums(false), validPC(false) + validExData(false), validCpuAndThreadNums(false), validPC(false) {} /** @@ -169,7 +174,7 @@ class Request validPaddr = true; validAsidVaddr = false; validPC = false; - validScResult = false; + validExData = false; mmapedIpr = false; } @@ -187,7 +192,7 @@ class Request validPaddr = false; validAsidVaddr = true; validPC = true; - validScResult = false; + validExData = false; mmapedIpr = false; } @@ -237,12 +242,12 @@ class Request void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; } /** Accessor function to check if sc result is valid. */ - bool scResultValid() { return validScResult; } + bool extraDataValid() { return validExData; } /** Accessor function for store conditional return value.*/ - uint64_t getScResult() { assert(validScResult); return scResult; } + uint64_t getExtraData() { assert(validExData); return extraData; } /** Accessor function for store conditional return value.*/ - void setScResult(uint64_t _scResult) - { scResult = _scResult; validScResult = true; } + void setExtraData(uint64_t _extraData) + { extraData = _extraData; validExData = true; } /** Accessor function for cpu number.*/ int getCpuNum() { assert(validCpuAndThreadNums); return cpuNum; } @@ -259,6 +264,12 @@ class Request bool isLocked() { return (getFlags() & LOCKED) != 0; } + bool isSwap() { return (getFlags() & MEM_SWAP || + getFlags() & MEM_SWAP_COND); } + + bool isCondSwap() { return (getFlags() & MEM_SWAP_COND) != 0; } + + friend class Packet; }; diff --git a/src/mem/tport.cc b/src/mem/tport.cc index c43c9aac0..b384a0444 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -68,7 +68,7 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) sendTiming(pkt, latency); } else { - if (pkt->cmd != Packet::UpgradeReq) + if (pkt->cmd != MemCmd::UpgradeReq) { delete pkt->req; delete pkt; diff --git a/src/mem/vport.cc b/src/mem/vport.cc index 8030c5a15..6cc4d9ca9 100644 --- a/src/mem/vport.cc +++ b/src/mem/vport.cc @@ -34,6 +34,7 @@ */ #include "base/chunk_generator.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" void @@ -70,3 +71,53 @@ VirtualPort::writeBlob(Addr addr, uint8_t *p, int size) } } +void +CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) +{ + uint8_t *dst = (uint8_t *)dest; + VirtualPort *vp = tc->getVirtPort(tc); + + vp->readBlob(src, dst, cplen); + + tc->delVirtPort(vp); + +} + +void +CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) +{ + uint8_t *src = (uint8_t *)source; + VirtualPort *vp = tc->getVirtPort(tc); + + vp->writeBlob(dest, src, cplen); + + tc->delVirtPort(vp); +} + +void +CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) +{ + int len = 0; + char *start = dst; + VirtualPort *vp = tc->getVirtPort(tc); + + do { + vp->readBlob(vaddr++, (uint8_t*)dst++, 1); + } while (len < maxlen && start[len++] != 0 ); + + tc->delVirtPort(vp); + dst[len] = 0; +} + +void +CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) +{ + VirtualPort *vp = tc->getVirtPort(tc); + for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done(); + gen.next()) + { + vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); + src += gen.size(); + } + tc->delVirtPort(vp); +} diff --git a/src/mem/vport.hh b/src/mem/vport.hh index c83836258..a8ceaa9fc 100644 --- a/src/mem/vport.hh +++ b/src/mem/vport.hh @@ -49,6 +49,7 @@ * simple address masking operation (such as alpha super page accesses). */ + class VirtualPort : public FunctionalPort { private: @@ -75,5 +76,11 @@ class VirtualPort : public FunctionalPort virtual void writeBlob(Addr addr, uint8_t *p, int size); }; + +void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen); +void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen); +void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); + #endif //__MEM_VPORT_HH__ |