diff options
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/Bridge.py | 4 | ||||
| -rw-r--r-- | src/mem/Bus.py | 7 | ||||
| -rw-r--r-- | src/mem/PhysicalMemory.py | 2 | ||||
| -rw-r--r-- | src/mem/cache/BaseCache.py | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 15 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 7 |
6 files changed, 26 insertions, 13 deletions
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index 38b344613..ea8684e1b 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -31,8 +31,8 @@ from MemObject import MemObject class Bridge(MemObject): type = 'Bridge' - slave = Port('Slave port') - master = Port('Master port') + slave = SlavePort('Slave port') + master = MasterPort('Master port') req_size = Param.Int(16, "The number of requests to buffer") resp_size = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") diff --git a/src/mem/Bus.py b/src/mem/Bus.py index fda91742f..91043da80 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -33,13 +33,14 @@ from MemObject import MemObject class Bus(MemObject): type = 'Bus' - port = VectorPort("vector port for connecting devices") + slave = VectorSlavePort("vector port for connecting masters") + master = VectorMasterPort("vector port for connecting slaves") bus_id = Param.Int(0, "blah") clock = Param.Clock("1GHz", "bus clock speed") header_cycles = Param.Int(1, "cycles of overhead per transaction") width = Param.Int(64, "bus width (bytes)") block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") - default = \ - Port("Default port for requests that aren't handled by a device.") + default = MasterPort("Default port for requests that aren't handled " \ + "by a device.") use_default_range = \ Param.Bool(False, "Query default port device for legal range.") diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py index 95cc73daa..c5f80b4c9 100644 --- a/src/mem/PhysicalMemory.py +++ b/src/mem/PhysicalMemory.py @@ -32,7 +32,7 @@ from MemObject import * class PhysicalMemory(MemObject): type = 'PhysicalMemory' - port = VectorPort("the access port") + port = VectorSlavePort("the access port") range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency('30ns', "latency of an access") diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 4389eb356..adc48a461 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -58,7 +58,7 @@ class BaseCache(MemObject): prefetch_on_access = Param.Bool(False, "notify the hardware prefetcher on every access (not just misses)") prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") - cpu_side = Port("Port on side closer to CPU") - mem_side = Port("Port on side closer to MEM") + cpu_side = SlavePort("Port on side closer to CPU") + mem_side = MasterPort("Port on side closer to MEM") addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index ab3e6e3b7..2ef65a13a 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -68,13 +68,24 @@ RubyPort::init() Port * RubyPort::getPort(const std::string &if_name, int idx) { - if (if_name == "port") { - M5Port* cpuPort = new M5Port(csprintf("%s-port%d", name(), idx), + // used by the CPUs to connect the caches to the interconnect, and + // for the x86 case also the interrupt master + if (if_name == "slave") { + M5Port* cpuPort = new M5Port(csprintf("%s-slave%d", name(), idx), this, ruby_system, access_phys_mem); cpu_ports.push_back(cpuPort); return cpuPort; } + // used by the x86 CPUs to connect the interrupt PIO and interrupt slave + // port + if (if_name == "master") { + PioPort* masterPort = new PioPort(csprintf("%s-master%d", name(), idx), + this); + + return masterPort; + } + if (if_name == "pio_port") { // ensure there is only one pio port assert(pio_port == NULL); diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index ddf760f7b..b1e17e052 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -34,11 +34,12 @@ from MemObject import MemObject class RubyPort(MemObject): type = 'RubyPort' abstract = True - port = VectorPort("M5 port") + slave = VectorSlavePort("CPU slave port") + master = VectorMasterPort("CPU master port") version = Param.Int(0, "") - pio_port = Port("Ruby_pio_port") + pio_port = MasterPort("Ruby_pio_port") physmem = Param.PhysicalMemory("") - physMemPort = Port("port to physical memory") + physMemPort = MasterPort("port to physical memory") using_ruby_tester = Param.Bool(False, "") using_network_tester = Param.Bool(False, "") access_phys_mem = Param.Bool(True, |