8 files changed, 11 insertions, 16 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a447ae3d5..56e7a4d58 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -53,8 +53,6 @@
 
 #include "sim/sim_events.hh" // for SimExitEvent
 
-using namespace std;
-
 template<class TagStore, class Buffering, class Coherence>
 bool
 Cache<TagStore,Buffering,Coherence>::
@@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
         MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 
         // There can be many matching outstanding writes.
-        vector<MSHR*> writes;
+        std::vector<MSHR*> writes;
         missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
 
         if (!update) {
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index 10d53b109..2f61e8a54 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -40,8 +40,6 @@
 #include "sim/eventq.hh" // for Event declaration.
 #include "mem/request.hh"
 
-using namespace TheISA;
-
 /**
  * @todo Move writebacks into shared BaseBuffer class.
  */
diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
index db5c94820..e554b3cec 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
@@ -33,6 +33,7 @@
  * Describes a tagged prefetcher based on template policies.
  */
 
+#include "arch/isa_traits.hh"
 #include "mem/cache/prefetch/tagged_prefetcher.hh"
 
 template <class TagStore, class Buffering>
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 534db0077..83b4006e2 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -39,7 +39,7 @@
 #define __MEM_PACKET_HH__
 
 #include "mem/request.hh"
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
 #include "sim/root.hh"
 #include <list>
 
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index a34a0393a..2b460306f 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -64,7 +64,7 @@ PageTable::~PageTable()
 }
 
 Fault
-PageTable::page_check(Addr addr, int size) const
+PageTable::page_check(Addr addr, int64_t size) const
 {
     if (size < sizeof(uint64_t)) {
         if (!isPowerOf2(size)) {
@@ -92,7 +92,7 @@ PageTable::page_check(Addr addr, int size) const
 
 
 void
-PageTable::allocate(Addr vaddr, int size)
+PageTable::allocate(Addr vaddr, int64_t size)
 {
     // starting address must be page aligned
     assert(pageOffset(vaddr) == 0);
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 12d4ec603..fce063280 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -38,7 +38,7 @@
 
 #include <string>
 
-#include "arch/faults.hh"
+#include "sim/faults.hh"
 #include "arch/isa_traits.hh"
 #include "base/hashmap.hh"
 #include "base/trace.hh"
@@ -77,9 +77,9 @@ class PageTable
     Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
     Addr pageOffset(Addr a) { return (a &  offsetMask); }
 
-    Fault page_check(Addr addr, int size) const;
+    Fault page_check(Addr addr, int64_t size) const;
 
-    void allocate(Addr vaddr, int size);
+    void allocate(Addr vaddr, int64_t size);
 
     /**
      * Translate function
diff --git a/src/mem/port_impl.hh b/src/mem/port_impl.hh
index e9a159293..b7980bdd2 100644
--- a/src/mem/port_impl.hh
+++ b/src/mem/port_impl.hh
@@ -28,8 +28,6 @@
  * Authors: Ali Saidi
  */
 
-#include "arch/isa_specific.hh"
-#include "arch/isa_traits.hh"
 #include "mem/port.hh"
 #include "sim/byteswap.hh"
 
@@ -37,7 +35,7 @@ template <typename T>
 void
 FunctionalPort::writeHtoG(Addr addr, T d)
 {
-    d = TheISA::htog(d);
+    d = htog(d);
     writeBlob(addr, (uint8_t*)&d, sizeof(T));
 }
 
@@ -48,6 +46,6 @@ FunctionalPort::readGtoH(Addr addr)
 {
     T d;
     readBlob(addr, (uint8_t*)&d, sizeof(T));
-    return TheISA::gtoh(d);
+    return gtoh(d);
 }
 
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 91b1c3408..457310298 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -39,7 +39,7 @@
 #ifndef __MEM_REQUEST_HH__
 #define __MEM_REQUEST_HH__
 
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
 #include "sim/root.hh"
 
 class Request;