diff options
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/SConscript | 4 | ||||
| -rw-r--r-- | src/mem/fs_translating_port_proxy.cc (renamed from src/mem/vport.cc) | 77 | ||||
| -rw-r--r-- | src/mem/fs_translating_port_proxy.hh (renamed from src/mem/vport.hh) | 73 | ||||
| -rw-r--r-- | src/mem/port.hh | 44 | ||||
| -rw-r--r-- | src/mem/port_proxy.hh | 174 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 7 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPortProxy.cc (renamed from src/mem/port_impl.hh) | 53 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPortProxy.hh | 114 | ||||
| -rw-r--r-- | src/mem/ruby/system/SConscript | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 3 | ||||
| -rw-r--r-- | src/mem/se_translating_port_proxy.cc (renamed from src/mem/translating_port.cc) | 54 | ||||
| -rw-r--r-- | src/mem/se_translating_port_proxy.hh (renamed from src/mem/translating_port.hh) | 48 |
12 files changed, 511 insertions, 141 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 50423fa67..dafc8c4a2 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -48,10 +48,10 @@ if env['TARGET_ISA'] != 'no': Source('physical.cc') if env['FULL_SYSTEM']: - Source('vport.cc') + Source('fs_translating_port_proxy.cc') elif env['TARGET_ISA'] != 'no': Source('page_table.cc') - Source('translating_port.cc') + Source('se_translating_port_proxy.cc') DebugFlag('Bus') DebugFlag('BusAddrRanges') diff --git a/src/mem/vport.cc b/src/mem/fs_translating_port_proxy.cc index ab061c019..d202b22bd 100644 --- a/src/mem/vport.cc +++ b/src/mem/fs_translating_port_proxy.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2006 The Regents of The University of Michigan * All rights reserved. * @@ -26,6 +38,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Ali Saidi + * Andreas Hansson */ /** @@ -34,49 +47,81 @@ */ #include "base/chunk_generator.hh" -#include "config/the_isa.hh" +#include "cpu/base.hh" #include "cpu/thread_context.hh" -#include "mem/vport.hh" +#include "mem/fs_translating_port_proxy.hh" + +using namespace TheISA; + +FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc) + : PortProxy(*(tc->getCpuPtr()->getPort("dcache_port"))), _tc(tc) +{ +} + +FSTranslatingPortProxy::FSTranslatingPortProxy(Port &port) + : PortProxy(port), _tc(NULL) +{ +} + +FSTranslatingPortProxy::~FSTranslatingPortProxy() +{ +} void -VirtualPort::readBlob(Addr addr, uint8_t *p, int size) +FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) { Addr paddr; for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done(); - gen.next()) + gen.next()) { - if (tc) - paddr = TheISA::vtophys(tc,gen.addr()); + if (_tc) + paddr = TheISA::vtophys(_tc,gen.addr()); else paddr = TheISA::vtophys(gen.addr()); - FunctionalPort::readBlob(paddr, p, gen.size()); + PortProxy::readBlob(paddr, p, gen.size()); p += gen.size(); } } void -VirtualPort::writeBlob(Addr addr, uint8_t *p, int size) +FSTranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) { Addr paddr; for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done(); - gen.next()) + gen.next()) { - if (tc) - paddr = TheISA::vtophys(tc,gen.addr()); + if (_tc) + paddr = TheISA::vtophys(_tc,gen.addr()); else paddr = TheISA::vtophys(gen.addr()); - FunctionalPort::writeBlob(paddr, p, gen.size()); + PortProxy::writeBlob(paddr, p, gen.size()); p += gen.size(); } } void +FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) +{ + Addr paddr; + for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done(); + gen.next()) + { + if (_tc) + paddr = TheISA::vtophys(_tc,gen.addr()); + else + paddr = TheISA::vtophys(gen.addr()); + + PortProxy::memsetBlob(paddr, v, gen.size()); + } +} + +void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) { uint8_t *dst = (uint8_t *)dest; - VirtualPort *vp = tc->getVirtPort(); + FSTranslatingPortProxy* vp = tc->getVirtProxy(); vp->readBlob(src, dst, cplen); } @@ -85,7 +130,7 @@ void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) { uint8_t *src = (uint8_t *)source; - VirtualPort *vp = tc->getVirtPort(); + FSTranslatingPortProxy* vp = tc->getVirtProxy(); vp->writeBlob(dest, src, cplen); } @@ -95,7 +140,7 @@ CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) { int len = 0; char *start = dst; - VirtualPort *vp = tc->getVirtPort(); + FSTranslatingPortProxy* vp = tc->getVirtProxy(); do { vp->readBlob(vaddr++, (uint8_t*)dst++, 1); @@ -107,7 +152,7 @@ CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) { - VirtualPort *vp = tc->getVirtPort(); + FSTranslatingPortProxy* vp = tc->getVirtProxy(); for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done(); gen.next()) { diff --git a/src/mem/vport.hh b/src/mem/fs_translating_port_proxy.hh index 1dfc0ea23..826def902 100644 --- a/src/mem/vport.hh +++ b/src/mem/fs_translating_port_proxy.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2006 The Regents of The University of Michigan * All rights reserved. * @@ -26,45 +38,49 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Ali Saidi + * Andreas Hansson */ /** * @file - * Virtual Port Object Declaration. These ports incorporate some translation - * into their access methods. Thus you can use one to read and write data - * to/from virtual addresses. + * TranslatingPortProxy Object Declaration for FS. + * + * Port proxies are used when non structural entities need access to + * the memory system. Proxy objects replace the previous + * FunctionalPort, TranslatingPort and VirtualPort objects, which + * provided the same functionality as the proxies, but were instances + * of ports not corresponding to real structural ports of the + * simulated system. Via the port proxies all the accesses go through + * an actual port and thus are transparent to a potentially + * distributed memory and automatically adhere to the memory map of + * the system. */ -#ifndef __MEM_VPORT_HH__ -#define __MEM_VPORT_HH__ +#ifndef __MEM_FS_PORT_PROXY_HH__ +#define __MEM_FS_PORT_PROXY_HH__ #include "arch/vtophys.hh" -#include "config/full_system.hh" -#include "mem/port_impl.hh" +#include "mem/port_proxy.hh" -/** A class that translates a virtual address to a physical address and then - * calls the above read/write functions. If a thread context is provided the - * address can alway be translated, If not it can only be translated if it is a - * simple address masking operation (such as alpha super page accesses). +/** + * A TranslatingPortProxy in FS mode translates a virtual address to a + * physical address and then calls the read/write functions of the + * port. If a thread context is provided the address can alway be + * translated, If not it can only be translated if it is a simple + * address masking operation (such as alpha super page accesses). */ - - -class VirtualPort : public FunctionalPort +class FSTranslatingPortProxy : public PortProxy { private: - ThreadContext *tc; + ThreadContext* _tc; public: - VirtualPort(const std::string &_name, ThreadContext *_tc = NULL) - : FunctionalPort(_name), tc(_tc) - {} - /** Return true if we have an thread context. This is used to - * prevent someone from accidently deleting the cpus statically - * allocated vport. - * @return true if a thread context isn't valid - */ - bool nullThreadContext() { return tc != NULL; } + FSTranslatingPortProxy(ThreadContext* tc); + + FSTranslatingPortProxy(Port &port); + + virtual ~FSTranslatingPortProxy(); /** Version of readblob that translates virt->phys and deals * with page boundries. */ @@ -73,13 +89,16 @@ class VirtualPort : public FunctionalPort /** Version of writeBlob that translates virt->phys and deals * with page boundries. */ virtual void writeBlob(Addr addr, uint8_t *p, int size); -}; + /** + * Fill size bytes starting at addr with byte value val. + */ + virtual void memsetBlob(Addr address, uint8_t v, int size); +}; void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen); void CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen); void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); -#endif //__MEM_VPORT_HH__ - +#endif //__MEM_FS_PORT_PROXY_HH__ diff --git a/src/mem/port.hh b/src/mem/port.hh index bb74bf497..c787f9f51 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -255,48 +255,4 @@ class Port : public EventManager void blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd); }; -/** A simple functional port that is only meant for one way communication to - * physical memory. It is only meant to be used to load data into memory before - * the simulation begins. - */ - -class FunctionalPort : public Port -{ - public: - FunctionalPort(const std::string &_name, MemObject *_owner = NULL) - : Port(_name, _owner) - {} - - protected: - virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir"); - M5_DUMMY_RETURN } - virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir"); - M5_DUMMY_RETURN } - virtual void recvFunctional(PacketPtr pkt) { panic("FuncPort is UniDir"); } - virtual void recvStatusChange(Status status) {} - - public: - /** a write function that also does an endian conversion. */ - template <typename T> - inline void writeHtoG(Addr addr, T d); - - /** a read function that also does an endian conversion. */ - template <typename T> - inline T readGtoH(Addr addr); - - template <typename T> - inline void write(Addr addr, T d) - { - writeBlob(addr, (uint8_t*)&d, sizeof(T)); - } - - template <typename T> - inline T read(Addr addr) - { - T d; - readBlob(addr, (uint8_t*)&d, sizeof(T)); - return d; - } -}; - #endif //__MEM_PORT_HH__ diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh new file mode 100644 index 000000000..31ad4c1cd --- /dev/null +++ b/src/mem/port_proxy.hh @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +/** + * @file + * PortProxy Object Declaration. + * + * Port proxies are used when non structural entities need access to + * the memory system. Proxy objects replace the previous + * FunctionalPort, TranslatingPort and VirtualPort objects, which + * provided the same functionality as the proxies, but were instances + * of ports not corresponding to real structural ports of the + * simulated system. Via the port proxies all the accesses go through + * an actual port and thus are transparent to a potentially + * distributed memory and automatically adhere to the memory map of + * the system. + */ + +#ifndef __MEM_PORT_PROXY_HH__ +#define __MEM_PORT_PROXY_HH__ + +#include "config/the_isa.hh" +#if THE_ISA != NO_ISA + #include "arch/isa_traits.hh" +#endif + +#include "base/types.hh" +#include "mem/port.hh" +#include "sim/byteswap.hh" + +/** + * This object is a proxy for a structural port, + * to be used for debug accesses. + * + * This proxy object is used when non structural entities + * (e.g. thread contexts, object file loaders) need access to the + * memory system. It calls the corresponding functions on the underlying + * structural port, and provides templatized convenience access functions. + * + * The addresses are interpreted as physical addresses. + * + * @sa SETranslatingProxy + * @sa FSTranslatingProxy + */ +class PortProxy +{ + protected: + Port &_port; + + public: + PortProxy(Port &port) : _port(port) { } + virtual ~PortProxy() { } + + public: + /** + * Read size bytes memory at address and store in p. + */ + virtual void readBlob(Addr address, uint8_t* p, int size) + { _port.readBlob(address, p, size); } + + /** + * Write size bytes from p to address. + */ + virtual void writeBlob(Addr address, uint8_t* p, int size) + { _port.writeBlob(address, p, size); } + + /** + * Fill size bytes starting at addr with byte value val. + */ + virtual void memsetBlob(Addr address, uint8_t v, int size) + { _port.memsetBlob(address, v, size); } + + /** + * Read sizeof(T) bytes from address and return as object T. + */ + template <typename T> + T read(Addr address); + + /** + * Write object T to address. Writes sizeof(T) bytes. + */ + template <typename T> + void write(Addr address, T data); + +#if THE_ISA != NO_ISA + /** + * Read sizeof(T) bytes from address and return as object T. + * Performs Guest to Host endianness transform. + */ + template <typename T> + T readGtoH(Addr address); + + /** + * Write object T to address. Writes sizeof(T) bytes. + * Performs Host to Guest endianness transform. + */ + template <typename T> + void writeHtoG(Addr address, T data); +#endif +}; + + +template <typename T> +T +PortProxy::read(Addr address) +{ + T data; + readBlob(address, (uint8_t*)&data, sizeof(T)); + return data; +} + +template <typename T> +void +PortProxy::write(Addr address, T data) +{ + writeBlob(address, (uint8_t*)&data, sizeof(T)); +} + +#if THE_ISA != NO_ISA +template <typename T> +T +PortProxy::readGtoH(Addr address) +{ + T data; + readBlob(address, (uint8_t*)&data, sizeof(T)); + return TheISA::gtoh(data); +} + +template <typename T> +void +PortProxy::writeHtoG(Addr address, T data) +{ + data = TheISA::htog(data); + writeBlob(address, (uint8_t*)&data, sizeof(T)); +} +#endif + +#endif // __MEM_PORT_PROXY_HH__ diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 64faf6aed..0b013f78e 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -464,8 +464,11 @@ RubyPort::M5Port::recvFunctional(PacketPtr pkt) // turn packet around to go back to requester if response expected if (needsResponse) { pkt->setFunctionalResponseStatus(accessSucceeded); - DPRINTF(RubyPort, "Sending packet back over port\n"); - sendFunctional(pkt); + + // @todo There should not be a reverse call since the response is + // communicated through the packet pointer + // DPRINTF(RubyPort, "Sending packet back over port\n"); + // sendFunctional(pkt); } DPRINTF(RubyPort, "Functional access %s!\n", accessSucceeded ? "successful":"failed"); diff --git a/src/mem/port_impl.hh b/src/mem/ruby/system/RubyPortProxy.cc index bc9592164..29a693ca6 100644 --- a/src/mem/port_impl.hh +++ b/src/mem/ruby/system/RubyPortProxy.cc @@ -1,6 +1,15 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are @@ -25,29 +34,37 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Ali Saidi + * Authors: Andreas Hansson */ -#include "arch/isa_traits.hh" -#include "config/the_isa.hh" -#include "mem/port.hh" -#include "sim/byteswap.hh" +#include "mem/ruby/system/RubyPortProxy.hh" -template <typename T> -void -FunctionalPort::writeHtoG(Addr addr, T d) +RubyPortProxy::RubyPortProxy(const RubyPortProxyParams* p) : + RubyPort(p) { +} + +RubyPortProxy::~RubyPortProxy() { - d = TheISA::htog(d); - writeBlob(addr, (uint8_t*)&d, sizeof(T)); } +void +RubyPortProxy::init() +{ + // Merely override to not care about the m_controller being NULL +} -template <typename T> -T -FunctionalPort::readGtoH(Addr addr) +RequestStatus +RubyPortProxy::makeRequest(PacketPtr pkt) { - T d; - readBlob(addr, (uint8_t*)&d, sizeof(T)); - return TheISA::gtoh(d); + // This sequencer should only be used through the functional + // accesses made by the system port and so simply fail if this + // happens. + panic("RubyPortProxy::makeRequest should not be called"); + return RequestStatus_NULL; } +RubyPortProxy* +RubyPortProxyParams::create() +{ + return new RubyPortProxy(this); +} diff --git a/src/mem/ruby/system/RubyPortProxy.hh b/src/mem/ruby/system/RubyPortProxy.hh new file mode 100644 index 000000000..8f88541e5 --- /dev/null +++ b/src/mem/ruby/system/RubyPortProxy.hh @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Hansson + */ + +/** + * @file + * RobyPortProxy for connecting system port to Ruby + * + * A trivial wrapper that allows the system port to connect to Ruby + * and use nothing but functional accesses. + */ + +#ifndef __MEM_RUBY_SYSTEM_RUBYPORTPROXY_HH__ +#define __MEM_RUBY_SYSTEM_RUBYPORTPROXY_HH__ + +#include "mem/ruby/system/RubyPort.hh" +#include "params/RubyPortProxy.hh" + +class RubyPortProxy : public RubyPort +{ + + public: + + /** + * Create a new RubyPortProxy. + * + * @param p Parameters inherited from the RubyPort + */ + RubyPortProxy(const RubyPortProxyParams* p); + + /** + * Destruct a RubyPortProxy. + */ + virtual ~RubyPortProxy(); + + /** + * Initialise a RubyPortProxy by doing nothing and avoid + * involving the super class. + */ + void init(); + + /** + * Pure virtual member in the super class that we are forced to + * implement even if it is never used (since there are only + * functional accesses). + * + * @param pkt The packet to serve to Ruby + * @returns always a NULL status + */ + RequestStatus makeRequest(PacketPtr pkt); + + /** + * Pure virtual member in the super class that we are forced to + * implement even if it is never used (since there are only + * functional accesses). + * + * @returns always 0 + */ + int outstandingCount() const { return 0; } + + /** + * Pure virtual member in the super class that we are forced to + * implement even if it is never used (since there are only + * functional accesses). + * + * @returns always false + */ + bool isDeadlockEventScheduled() const { return false; } + + /** + * Pure virtual member in the super class that we are forced to + * implement even if it is never used (since there are only + * functional accesses). + */ + void descheduleDeadlockEvent() { } + +}; + +#endif // __MEM_RUBY_SYSTEM_RUBYPORTPROXY_HH__ diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript index 66d7d95bb..cbb1da3b1 100644 --- a/src/mem/ruby/system/SConscript +++ b/src/mem/ruby/system/SConscript @@ -49,6 +49,7 @@ Source('WireBuffer.cc') Source('MemoryNode.cc') Source('PersistentTable.cc') Source('RubyPort.cc') +Source('RubyPortProxy.cc') Source('Sequencer.cc') Source('System.cc') Source('TimerTable.cc') diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 5d56dc000..ddf760f7b 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -44,6 +44,9 @@ class RubyPort(MemObject): access_phys_mem = Param.Bool(True, "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") + +class RubyPortProxy(RubyPort): + type = 'RubyPortProxy' class RubySequencer(RubyPort): type = 'RubySequencer' diff --git a/src/mem/translating_port.cc b/src/mem/se_translating_port_proxy.cc index 3ea728349..027930287 100644 --- a/src/mem/translating_port.cc +++ b/src/mem/se_translating_port_proxy.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2001-2005 The Regents of The University of Michigan * All rights reserved. * @@ -27,6 +39,7 @@ * * Authors: Ron Dreslinski * Steve Reinhardt + * Andreas Hansson */ #include <string> @@ -34,23 +47,22 @@ #include "base/chunk_generator.hh" #include "config/the_isa.hh" #include "mem/page_table.hh" -#include "mem/port.hh" -#include "mem/translating_port.hh" +#include "mem/se_translating_port_proxy.hh" #include "sim/process.hh" using namespace TheISA; -TranslatingPort::TranslatingPort(const std::string &_name, - Process *p, AllocType alloc) - : FunctionalPort(_name), pTable(p->pTable), process(p), +SETranslatingPortProxy::SETranslatingPortProxy(Port& port, Process *p, + AllocType alloc) + : PortProxy(port), pTable(p->pTable), process(p), allocating(alloc) { } -TranslatingPort::~TranslatingPort() +SETranslatingPortProxy::~SETranslatingPortProxy() { } bool -TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size) +SETranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) { Addr paddr; int prevSize = 0; @@ -60,7 +72,7 @@ TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size) if (!pTable->translate(gen.addr(),paddr)) return false; - Port::readBlob(paddr, p + prevSize, gen.size()); + PortProxy::readBlob(paddr, p + prevSize, gen.size()); prevSize += gen.size(); } @@ -68,7 +80,7 @@ TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size) } void -TranslatingPort::readBlob(Addr addr, uint8_t *p, int size) +SETranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) { if (!tryReadBlob(addr, p, size)) fatal("readBlob(0x%x, ...) failed", addr); @@ -76,7 +88,7 @@ TranslatingPort::readBlob(Addr addr, uint8_t *p, int size) bool -TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) +SETranslatingPortProxy::tryWriteBlob(Addr addr, uint8_t *p, int size) { Addr paddr; @@ -99,7 +111,7 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) pTable->translate(gen.addr(), paddr); } - Port::writeBlob(paddr, p + prevSize, gen.size()); + PortProxy::writeBlob(paddr, p + prevSize, gen.size()); prevSize += gen.size(); } @@ -108,14 +120,14 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) void -TranslatingPort::writeBlob(Addr addr, uint8_t *p, int size) +SETranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) { if (!tryWriteBlob(addr, p, size)) fatal("writeBlob(0x%x, ...) failed", addr); } bool -TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) +SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) { Addr paddr; @@ -131,14 +143,14 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) } } - Port::memsetBlob(paddr, val, gen.size()); + PortProxy::memsetBlob(paddr, val, gen.size()); } return true; } void -TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size) +SETranslatingPortProxy::memsetBlob(Addr addr, uint8_t val, int size) { if (!tryMemsetBlob(addr, val, size)) fatal("memsetBlob(0x%x, ...) failed", addr); @@ -146,7 +158,7 @@ TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size) bool -TranslatingPort::tryWriteString(Addr addr, const char *str) +SETranslatingPortProxy::tryWriteString(Addr addr, const char *str) { Addr paddr,vaddr; uint8_t c; @@ -158,21 +170,21 @@ TranslatingPort::tryWriteString(Addr addr, const char *str) if (!pTable->translate(vaddr++,paddr)) return false; - Port::writeBlob(paddr, &c, 1); + PortProxy::writeBlob(paddr, &c, 1); } while (c); return true; } void -TranslatingPort::writeString(Addr addr, const char *str) +SETranslatingPortProxy::writeString(Addr addr, const char *str) { if (!tryWriteString(addr, str)) fatal("writeString(0x%x, ...) failed", addr); } bool -TranslatingPort::tryReadString(std::string &str, Addr addr) +SETranslatingPortProxy::tryReadString(std::string &str, Addr addr) { Addr paddr,vaddr; uint8_t c; @@ -183,7 +195,7 @@ TranslatingPort::tryReadString(std::string &str, Addr addr) if (!pTable->translate(vaddr++,paddr)) return false; - Port::readBlob(paddr, &c, 1); + PortProxy::readBlob(paddr, &c, 1); str += c; } while (c); @@ -191,7 +203,7 @@ TranslatingPort::tryReadString(std::string &str, Addr addr) } void -TranslatingPort::readString(std::string &str, Addr addr) +SETranslatingPortProxy::readString(std::string &str, Addr addr) { if (!tryReadString(str, addr)) fatal("readString(0x%x, ...) failed", addr); diff --git a/src/mem/translating_port.hh b/src/mem/se_translating_port_proxy.hh index 76c7947be..71e8b4f50 100644 --- a/src/mem/translating_port.hh +++ b/src/mem/se_translating_port_proxy.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2001-2005 The Regents of The University of Michigan * All rights reserved. * @@ -27,18 +39,33 @@ * * Authors: Ron Dreslinski * Ali Saidi + * Andreas Hansson */ -#ifndef __MEM_TRANSLATING_PROT_HH__ -#define __MEM_TRANSLATING_PROT_HH__ - -#include "mem/port.hh" +#ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__ +#define __MEM_SE_TRANSLATING_PORT_PROXY_HH__ -class PageTable; -class Process; +#include "mem/page_table.hh" +#include "mem/port_proxy.hh" +#include "sim/process.hh" -class TranslatingPort : public FunctionalPort +/** + * @file + * TranslatingPortProxy Object Declaration for SE. + * + * Port proxies are used when non structural entities need access to + * the memory system. Proxy objects replace the previous + * FunctionalPort, TranslatingPort and VirtualPort objects, which + * provided the same functionality as the proxies, but were instances + * of ports not corresponding to real structural ports of the + * simulated system. Via the port proxies all the accesses go through + * an actual port and thus are transparent to a potentially + * distributed memory and automatically adhere to the memory map of + * the system. + */ +class SETranslatingPortProxy : public PortProxy { + public: enum AllocType { Always, @@ -52,9 +79,8 @@ class TranslatingPort : public FunctionalPort AllocType allocating; public: - TranslatingPort(const std::string &_name, - Process *p, AllocType alloc); - virtual ~TranslatingPort(); + SETranslatingPortProxy(Port& port, Process* p, AllocType alloc); + virtual ~SETranslatingPortProxy(); bool tryReadBlob(Addr addr, uint8_t *p, int size); bool tryWriteBlob(Addr addr, uint8_t *p, int size); @@ -70,4 +96,4 @@ class TranslatingPort : public FunctionalPort void readString(std::string &str, Addr addr); }; -#endif +#endif // __MEM_SE_TRANSLATING_PORT_PROXY_HH__ |