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-rw-r--r--src/mem/cache/base_cache.cc4
-rw-r--r--src/mem/cache/cache_impl.hh8
-rw-r--r--src/mem/physical.cc12
-rw-r--r--src/mem/tport.cc13
-rw-r--r--src/mem/tport.hh2
5 files changed, 20 insertions, 19 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index ec9e1cf9b..b44468486 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -81,9 +81,9 @@ BaseCache::CachePort::deviceBlockSize()
void
BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt)
{
- checkFunctional(pkt);
- if (!pkt->isResponse())
+ if (!checkFunctional(pkt)) {
sendFunctional(pkt);
+ }
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index c1b01d676..d144266ed 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1253,9 +1253,9 @@ template<class TagStore>
void
Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
{
- checkFunctional(pkt);
- if (!pkt->isResponse())
+ if (!checkFunctional(pkt)) {
myCache()->functionalAccess(pkt, cache->memSidePort);
+ }
}
@@ -1327,9 +1327,9 @@ template<class TagStore>
void
Cache<TagStore>::MemSidePort::recvFunctional(PacketPtr pkt)
{
- checkFunctional(pkt);
- if (!pkt->isResponse())
+ if (!checkFunctional(pkt)) {
myCache()->functionalAccess(pkt, cache->cpuSidePort);
+ }
}
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index b96fb8a56..2f358daf2 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -400,12 +400,12 @@ PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt)
void
PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
- checkFunctional(pkt);
-
- // Default implementation of SimpleTimingPort::recvFunctional()
- // calls recvAtomic() and throws away the latency; we can save a
- // little here by just not calculating the latency.
- memory->doFunctionalAccess(pkt);
+ if (!checkFunctional(pkt)) {
+ // Default implementation of SimpleTimingPort::recvFunctional()
+ // calls recvAtomic() and throws away the latency; we can save a
+ // little here by just not calculating the latency.
+ memory->doFunctionalAccess(pkt);
+ }
}
unsigned int
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index e4b8d70e9..b1a6a4813 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -30,7 +30,7 @@
#include "mem/tport.hh"
-void
+bool
SimpleTimingPort::checkFunctional(PacketPtr pkt)
{
DeferredPacketIterator i = transmitList.begin();
@@ -41,19 +41,20 @@ SimpleTimingPort::checkFunctional(PacketPtr pkt)
// If the target contains data, and it overlaps the
// probed request, need to update data
if (pkt->checkFunctional(target)) {
- return;
+ return true;
}
}
+
+ return false;
}
void
SimpleTimingPort::recvFunctional(PacketPtr pkt)
{
- checkFunctional(pkt);
-
- // Just do an atomic access and throw away the returned latency
- if (!pkt->isResponse())
+ if (!checkFunctional(pkt)) {
+ // Just do an atomic access and throw away the returned latency
recvAtomic(pkt);
+ }
}
bool
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index bc9da6c44..d0f1be425 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -99,7 +99,7 @@ class SimpleTimingPort : public Port
/** Check the list of buffered packets against the supplied
* functional request. */
- void checkFunctional(PacketPtr funcPkt);
+ bool checkFunctional(PacketPtr funcPkt);
/** Check whether we have a packet ready to go on the transmit list. */
bool deferredPacketReady()