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-rw-r--r--src/mem/SConscript7
-rw-r--r--src/mem/cache/SConscript5
-rw-r--r--src/mem/cache/tags/SConscript4
3 files changed, 16 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index bbb1e96fe..b572f703c 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -49,3 +49,10 @@ if env['FULL_SYSTEM']:
else:
Source('page_table.cc')
Source('translating_port.cc')
+
+TraceFlag('Bus')
+TraceFlag('BusAddrRanges')
+TraceFlag('BusBridge')
+TraceFlag('LLSC')
+TraceFlag('MMU')
+TraceFlag('MemoryAccess')
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 546e037bd..5ac7e34ad 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -35,3 +35,8 @@ SimObject('BaseCache.py')
Source('base_cache.cc')
Source('cache.cc')
Source('cache_builder.cc')
+
+TraceFlag('Cache')
+TraceFlag('CachePort')
+TraceFlag('CacheRepl')
+TraceFlag('HWPrefetch')
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index a65c44f22..18ed8408b 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -40,3 +40,7 @@ Source('split_lru.cc')
SimObject('Repl.py')
Source('repl/gen.cc')
+
+TraceFlag('IIC')
+TraceFlag('IICMore')
+TraceFlag('Split')