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-rw-r--r--src/mem/cache/cache.hh2
-rw-r--r--src/mem/cache/mshr.hh1
-rw-r--r--src/mem/cache/tags/lru.hh1
-rw-r--r--src/mem/coherent_bus.hh1
-rw-r--r--src/mem/simple_mem.hh1
5 files changed, 5 insertions, 1 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 9bdbd3456..3c34c10f7 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -64,7 +64,7 @@ class BasePrefetcher;
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore.
+ * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
*/
template <class TagStore>
class Cache : public BaseCache
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 7920ad717..87e561ac7 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -47,6 +47,7 @@ class MSHRQueue;
/**
* Miss Status and handling Register. This class keeps all the information
* needed to handle a cache miss including a list of target requests.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
*/
class MSHR : public Packet::SenderState, public Printable
{
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index bb1420f71..7938fcc3c 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -50,6 +50,7 @@ class CacheSet;
/**
* A LRU cache tag store.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
*/
class LRU : public BaseTags
{
diff --git a/src/mem/coherent_bus.hh b/src/mem/coherent_bus.hh
index a28b388d5..8941d0271 100644
--- a/src/mem/coherent_bus.hh
+++ b/src/mem/coherent_bus.hh
@@ -63,6 +63,7 @@
* The coherent bus can be used as a template for modelling QPI,
* HyperTransport, ACE and coherent OCP buses, and is typically used
* for the L1-to-L2 buses and as the main system interconnect.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
*/
class CoherentBus : public BaseBus
{
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 4f7af864b..f201709c2 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -58,6 +58,7 @@
* an configurable throughput and latency, potentially with a variance
* added to the latter. It uses a QueueSlavePort to avoid dealing with
* the flow control of sending responses.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
*/
class SimpleMemory : public AbstractMemory
{