diff options
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/cache/base_cache.hh | 2 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index fcc040bd9..46414974b 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -126,7 +126,7 @@ class BaseCache : public MemObject void requestBus(RequestCause cause, Tick time) { - DPRINTF(Cache, "Asserting bus request for cause %d\n", cause); + DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); if (!waitingOnRetry) { schedSendEvent(time); } diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 320e0be81..b159df84a 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1238,7 +1238,8 @@ Cache<TagStore>::MemSidePort::sendPacket() MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); bool success = sendTiming(pkt); - DPRINTF(Cache, "Address %x was %s in sending the timing request\n", + DPRINTF(CachePort, + "Address %x was %s in sending the timing request\n", pkt->getAddr(), success ? "successful" : "unsuccessful"); waitingOnRetry = !success; |