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-rw-r--r--src/mem/cache/base.hh5
-rw-r--r--src/mem/cache/tags/iic.cc2
-rw-r--r--src/mem/cache/tags/iic_repl/gen.cc2
-rw-r--r--src/mem/cache/tags/iic_repl/gen.hh2
-rw-r--r--src/mem/cache/tags/iic_repl/repl.hh2
-rw-r--r--src/mem/packet.hh2
-rw-r--r--src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc11
-rw-r--r--src/mem/ruby/system/Sequencer.hh2
8 files changed, 14 insertions, 14 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index df72e197f..3020613ca 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -73,6 +73,7 @@ class BaseCache : public MemObject
MSHRQueue_WriteBuffer
};
+ public:
/**
* Reasons for caches to be blocked.
*/
@@ -83,7 +84,6 @@ class BaseCache : public MemObject
NUM_BLOCKED_CAUSES
};
- public:
/**
* Reasons for cache to request a bus.
*/
@@ -94,7 +94,7 @@ class BaseCache : public MemObject
NUM_REQUEST_CAUSES
};
- private:
+ protected:
class CachePort : public SimpleTimingPort
{
@@ -138,7 +138,6 @@ class BaseCache : public MemObject
}
};
- public: //Made public so coherence can get at it.
CachePort *cpuSidePort;
CachePort *memSidePort;
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 71c3ba48c..acce3ffc8 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -187,7 +187,7 @@ IIC::regStats(const string &name)
.flags(pdf)
;
- repl->regStats(name);
+ repl->regStatsWithSuffix(name);
if (PROFILE_IIC)
setAccess
diff --git a/src/mem/cache/tags/iic_repl/gen.cc b/src/mem/cache/tags/iic_repl/gen.cc
index 7a1e7a110..137130b27 100644
--- a/src/mem/cache/tags/iic_repl/gen.cc
+++ b/src/mem/cache/tags/iic_repl/gen.cc
@@ -184,7 +184,7 @@ GenRepl::add(unsigned long tag_index)
}
void
-GenRepl::regStats(const string name)
+GenRepl::regStatsWithSuffix(const string name)
{
using namespace Stats;
diff --git a/src/mem/cache/tags/iic_repl/gen.hh b/src/mem/cache/tags/iic_repl/gen.hh
index fe105d95a..cbd15a6fd 100644
--- a/src/mem/cache/tags/iic_repl/gen.hh
+++ b/src/mem/cache/tags/iic_repl/gen.hh
@@ -209,7 +209,7 @@ class GenRepl : public Repl
* Register statistics.
* @param name The name to prepend to statistic descriptions.
*/
- virtual void regStats(const std::string name);
+ virtual void regStatsWithSuffix(const std::string name);
/**
* Update the tag pointer to when the tag moves.
diff --git a/src/mem/cache/tags/iic_repl/repl.hh b/src/mem/cache/tags/iic_repl/repl.hh
index 994af5164..51d8169e9 100644
--- a/src/mem/cache/tags/iic_repl/repl.hh
+++ b/src/mem/cache/tags/iic_repl/repl.hh
@@ -102,7 +102,7 @@ class Repl : public SimObject
* Register statistics.
* @param name The name to prepend to statistic descriptions.
*/
- virtual void regStats(const std::string name) = 0;
+ virtual void regStatsWithSuffix(const std::string name) = 0;
/**
* Update the tag pointer to when the tag moves.
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index e49ce7577..ce5748c24 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -53,7 +53,7 @@
#include "mem/request.hh"
#include "sim/core.hh"
-struct Packet;
+class Packet;
typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;
typedef std::list<PacketPtr> PacketList;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
index aee05b696..126c5c811 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
@@ -104,11 +104,12 @@ GarnetNetwork_d::init()
for (vector<Router_d*>::const_iterator i= m_router_ptr_vector.begin();
i != m_router_ptr_vector.end(); ++i) {
Router_d* router = safe_cast<Router_d*>(*i);
- int router_id=fault_model->declare_router(router->get_num_inports(),
- router->get_num_outports(),
- router->get_vc_per_vnet(),
- getBuffersPerDataVC(),
- getBuffersPerCtrlVC());
+ int router_id M5_VAR_USED =
+ fault_model->declare_router(router->get_num_inports(),
+ router->get_num_outports(),
+ router->get_vc_per_vnet(),
+ getBuffersPerDataVC(),
+ getBuffersPerCtrlVC());
assert(router_id == router->get_id());
router->printAggregateFaultProbability(cout);
router->printFaultVector(cout);
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index e262e32e8..296258994 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -41,7 +41,7 @@
class DataBlock;
class CacheMemory;
-class RubySequencerParams;
+struct RubySequencerParams;
struct SequencerRequest
{