diff options
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/bridge.cc | 4 | ||||
| -rw-r--r-- | src/mem/bus.cc | 2 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyMemoryControl.cc | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index 1a8437aa1..91bef2757 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -277,7 +277,7 @@ Bridge::BridgeMasterPort::trySendTiming() req = transmitList.front(); DPRINTF(Bridge, "Scheduling next send\n"); bridge.schedule(sendEvent, std::max(req.tick, - bridge.nextCycle())); + bridge.clockEdge())); } // if we have stalled a request due to a full request queue, @@ -318,7 +318,7 @@ Bridge::BridgeSlavePort::trySendTiming() resp = transmitList.front(); DPRINTF(Bridge, "Scheduling next send\n"); bridge.schedule(sendEvent, std::max(resp.tick, - bridge.nextCycle())); + bridge.clockEdge())); } // if there is space in the request queue and we were stalling diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 368d49c86..8546df565 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -135,7 +135,7 @@ BaseBus::calcPacketTiming(PacketPtr pkt) // the bus will be called at a time that is not necessarily // coinciding with its own clock, so start by determining how long // until the next clock edge (could be zero) - Tick offset = nextCycle() - curTick(); + Tick offset = clockEdge() - curTick(); // determine how many cycles are needed to send the data unsigned dataCycles = pkt->hasData() ? divCeil(pkt->getSize(), width) : 0; diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc index 75e6e1b06..5ffc60e2b 100644 --- a/src/mem/ruby/system/RubyMemoryControl.cc +++ b/src/mem/ruby/system/RubyMemoryControl.cc @@ -307,7 +307,7 @@ RubyMemoryControl::enqueueMemRef(MemoryNode& memRef) m_input_queue.push_back(memRef); if (!m_event.scheduled()) { - schedule(m_event, nextCycle()); + schedule(m_event, clockEdge()); } } |