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-rw-r--r--src/mem/protocol/Network_test-cache.sm218
-rw-r--r--src/mem/protocol/Network_test-dir.sm136
-rw-r--r--src/mem/protocol/Network_test-msg.sm77
-rw-r--r--src/mem/protocol/Network_test.slicc4
-rw-r--r--src/mem/protocol/SConsopts1
-rw-r--r--src/mem/ruby/network/garnet/BaseGarnetNetwork.cc1
-rw-r--r--src/mem/ruby/network/garnet/BaseGarnetNetwork.hh3
-rw-r--r--src/mem/ruby/network/garnet/BaseGarnetNetwork.py1
-rw-r--r--src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc14
-rw-r--r--src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc9
-rw-r--r--src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc8
-rw-r--r--src/mem/ruby/system/Sequencer.cc8
-rw-r--r--src/mem/ruby/system/Sequencer.hh2
-rw-r--r--src/mem/ruby/system/Sequencer.py1
14 files changed, 459 insertions, 24 deletions
diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
new file mode 100644
index 000000000..603c1f5f9
--- /dev/null
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2009 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Authors: Brad Beckmann
+ * Tushar Krishna
+ */
+
+
+machine(L1Cache, "Network_test L1 Cache")
+: Sequencer * sequencer,
+ int issue_latency = 2
+{
+
+ // NETWORK BUFFERS
+ MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false";
+ MessageBuffer forwardFromCache, network="To", virtual_network="1", ordered="false";
+ MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false";
+
+ // STATES
+ state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
+ I, AccessPermission:Invalid, desc="Not Present/Invalid";
+ }
+
+ // EVENTS
+ enumeration(Event, desc="Cache events") {
+ // From processor
+ Request, desc="Request from Network_test";
+ Forward, desc="Forward from Network_test";
+ Response, desc="Response from Network_test";
+ }
+
+ // STRUCTURE DEFINITIONS
+
+ MessageBuffer mandatoryQueue, ordered="false";
+ DataBlock dummyData;
+
+
+ // CacheEntry
+ structure(Entry, desc="...", interface="AbstractCacheEntry") {
+ State CacheState, desc="cache state";
+ DataBlock DataBlk, desc="Data in the block";
+ }
+
+ // TBE fields
+ structure(TBE, desc="...") {
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
+ }
+
+ structure(TBETable, external="yes") {
+ TBE lookup(Address);
+ void allocate(Address);
+ void deallocate(Address);
+ bool isPresent(Address);
+ }
+
+
+ // STRUCTURES
+
+ TBETable TBEs, template_hack="<L1Cache_TBE>";
+
+
+ // FUNCTIONS
+
+ // cpu/testers/networktest/networktest.cc generates packets of the type
+ // ReadReq, INST_FETCH, and WriteReq.
+ // These are converted to LD, IFETCH and ST by mem/ruby/system/RubyPort.cc.
+ // These are then sent to the sequencer, which sends them here.
+ // Network_test-cache.sm tags LD, IFETCH and ST as Request, Forward,
+ // and Response Events respectively, which are then injected into
+ // virtual networks 0, 1 and 2 respectively.
+ // This models traffic of different types within the network.
+ //
+ // Note that requests and forwards are MessageSizeType:Control,
+ // while responses are MessageSizeType:Data.
+ //
+ Event mandatory_request_type_to_event(RubyRequestType type) {
+ if (type == RubyRequestType:LD) {
+ return Event:Request;
+ } else if (type == RubyRequestType:IFETCH) {
+ return Event:Forward;
+ } else if (type == RubyRequestType:ST) {
+ return Event:Response;
+ } else {
+ error("Invalid RubyRequestType");
+ }
+ }
+
+
+ State getState(TBE tbe, Entry cache_entry, Address addr) {
+ return State:I;
+ }
+
+ void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+
+ }
+
+ Entry getCacheEntry(Address address), return_by_pointer="yes" {
+ return OOD;
+ }
+
+
+ // NETWORK PORTS
+
+ out_port(requestNetwork_out, RequestMsg, requestFromCache);
+ out_port(forwardNetwork_out, RequestMsg, forwardFromCache);
+ out_port(responseNetwork_out, RequestMsg, responseFromCache);
+
+ // Mandatory Queue
+ in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
+ if (mandatoryQueue_in.isReady()) {
+ peek(mandatoryQueue_in, CacheMsg) {
+ trigger(mandatory_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ getCacheEntry(in_msg.LineAddress),
+ TBEs[in_msg.LineAddress]);
+ }
+ }
+ }
+
+ // ACTIONS
+
+ // The destination directory of the packets is embedded in the address
+ // map_Address_to_Directory is used to retrieve it.
+
+ action(a_issueRequest, "a", desc="Issue a request") {
+ enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceRequestType:MSG;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ //out_msg.Destination := broadcast(MachineType:Directory);
+ out_msg.MessageSize := MessageSizeType:Control;
+ }
+ }
+
+ action(b_issueForward, "b", desc="Issue a forward") {
+ enqueue(forwardNetwork_out, RequestMsg, latency=issue_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceRequestType:MSG;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.MessageSize := MessageSizeType:Control;
+ }
+ }
+
+ action(c_issueResponse, "c", desc="Issue a response") {
+ enqueue(responseNetwork_out, RequestMsg, latency=issue_latency) {
+ out_msg.Address := address;
+ out_msg.Type := CoherenceRequestType:MSG;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.MessageSize := MessageSizeType:Data;
+ }
+ }
+
+ action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") {
+ mandatoryQueue_in.dequeue();
+ }
+
+ action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
+ sequencer.readCallback(address, dummyData);
+ }
+
+ action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
+ sequencer.writeCallback(address, dummyData);
+ }
+
+
+ // TRANSITIONS
+
+ // sequencer hit call back is performed after injecting the packets.
+ // The goal of the Network_test protocol is only to inject packets into
+ // the network, not to keep track of them via TBEs.
+
+ transition(I, Response) {
+ s_store_hit;
+ c_issueResponse;
+ m_popMandatoryQueue;
+ }
+
+ transition(I, Request) {
+ r_load_hit;
+ a_issueRequest;
+ m_popMandatoryQueue;
+ }
+ transition(I, Forward) {
+ r_load_hit;
+ b_issueForward;
+ m_popMandatoryQueue;
+ }
+
+}
diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm
new file mode 100644
index 000000000..6d2bbf359
--- /dev/null
+++ b/src/mem/protocol/Network_test-dir.sm
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2009 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Authors: Brad Beckmann
+ * Tushar Krishna
+ */
+
+
+machine(Directory, "Network_test Directory")
+:
+{
+
+ MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false";
+ MessageBuffer forwardToDir, network="From", virtual_network="1", ordered="false";
+ MessageBuffer responseToDir, network="From", virtual_network="2", ordered="false";
+
+ // STATES
+ state_declaration(State, desc="Directory states", default="Directory_State_I") {
+ // Base states
+ I, AccessPermission:Invalid, desc="Invalid";
+ }
+
+ // Events
+ enumeration(Event, desc="Directory events") {
+ // processor requests
+ Receive_Request, desc="Receive Message";
+ Receive_Forward, desc="Receive Message";
+ Receive_Response, desc="Receive Message";
+ }
+
+ // TYPES
+ // DirectoryEntry
+ structure(Entry, desc="...") {
+ State DirectoryState, desc="Directory state";
+ DataBlock DataBlk, desc="data for the block";
+ }
+
+ // ** OBJECTS **
+ State getState(Address addr) {
+ return State:I;
+ }
+
+ void setState(Address addr, State state) {
+
+ }
+
+ // ** IN_PORTS **
+
+ in_port(requestQueue_in, RequestMsg, requestToDir) {
+ if (requestQueue_in.isReady()) {
+ peek(requestQueue_in, RequestMsg) {
+ if (in_msg.Type == CoherenceRequestType:MSG) {
+ trigger(Event:Receive_Request, in_msg.Address);
+ } else {
+ error("Invalid message");
+ }
+ }
+ }
+ }
+ in_port(forwardQueue_in, RequestMsg, forwardToDir) {
+ if (forwardQueue_in.isReady()) {
+ peek(forwardQueue_in, RequestMsg) {
+ if (in_msg.Type == CoherenceRequestType:MSG) {
+ trigger(Event:Receive_Forward, in_msg.Address);
+ } else {
+ error("Invalid message");
+ }
+ }
+ }
+ }
+ in_port(responseQueue_in, RequestMsg, responseToDir) {
+ if (responseQueue_in.isReady()) {
+ peek(responseQueue_in, RequestMsg) {
+ if (in_msg.Type == CoherenceRequestType:MSG) {
+ trigger(Event:Receive_Response, in_msg.Address);
+ } else {
+ error("Invalid message");
+ }
+ }
+ }
+ }
+
+ // Actions
+
+ action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
+ requestQueue_in.dequeue();
+ }
+
+ action(f_popIncomingForwardQueue, "f", desc="Pop incoming forward queue") {
+ forwardQueue_in.dequeue();
+ }
+
+ action(r_popIncomingResponseQueue, "r", desc="Pop incoming response queue") {
+ responseQueue_in.dequeue();
+ }
+
+ // TRANSITIONS
+
+ // The directory simply drops the received packets.
+ // The goal of Network_test is only to track network stats.
+
+ transition(I, Receive_Request) {
+ i_popIncomingRequestQueue;
+ }
+ transition(I, Receive_Forward) {
+ f_popIncomingForwardQueue;
+ }
+ transition(I, Receive_Response) {
+ r_popIncomingResponseQueue;
+ }
+}
diff --git a/src/mem/protocol/Network_test-msg.sm b/src/mem/protocol/Network_test-msg.sm
new file mode 100644
index 000000000..7de35f176
--- /dev/null
+++ b/src/mem/protocol/Network_test-msg.sm
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2009 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+// CoherenceRequestType
+enumeration(CoherenceRequestType, desc="...") {
+ MSG, desc="Message";
+}
+
+// RequestMsg (and also forwarded requests)
+structure(RequestMsg, desc="...", interface="NetworkMessage") {
+ Address Address, desc="Physical address for this request";
+ CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
+ MachineID Requestor, desc="Node who initiated the request";
+ NetDest Destination, desc="Multicast destination mask";
+ DataBlock DataBlk, desc="data for the cache line";
+ MessageSizeType MessageSize, desc="size category of the message";
+}
+
+
+enumeration(DMARequestType, desc="...", default="DMARequestType_NULL") {
+ READ, desc="Memory Read";
+ WRITE, desc="Memory Write";
+ NULL, desc="Invalid";
+}
+
+enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
+ DATA, desc="DATA read";
+ ACK, desc="ACK write";
+ NULL, desc="Invalid";
+}
+
+structure(DMARequestMsg, desc="...", interface="NetworkMessage") {
+ DMARequestType Type, desc="Request type (read/write)";
+ Address PhysicalAddress, desc="Physical address for this request";
+ Address LineAddress, desc="Line address for this request";
+ NetDest Destination, desc="Destination";
+ DataBlock DataBlk, desc="DataBlk attached to this request";
+ int Len, desc="The length of the request";
+ MessageSizeType MessageSize, desc="size category of the message";
+}
+
+structure(DMAResponseMsg, desc="...", interface="NetworkMessage") {
+ DMAResponseType Type, desc="Response type (DATA/ACK)";
+ Address PhysicalAddress, desc="Physical address for this request";
+ Address LineAddress, desc="Line address for this request";
+ NetDest Destination, desc="Destination";
+ DataBlock DataBlk, desc="DataBlk attached to this request";
+ MessageSizeType MessageSize, desc="size category of the message";
+}
+
+
diff --git a/src/mem/protocol/Network_test.slicc b/src/mem/protocol/Network_test.slicc
new file mode 100644
index 000000000..9629a385c
--- /dev/null
+++ b/src/mem/protocol/Network_test.slicc
@@ -0,0 +1,4 @@
+Network_test-msg.sm
+Network_test-cache.sm
+Network_test-dir.sm
+standard_1level_CMP-protocol.sm
diff --git a/src/mem/protocol/SConsopts b/src/mem/protocol/SConsopts
index 0e794d5f0..dac52d742 100644
--- a/src/mem/protocol/SConsopts
+++ b/src/mem/protocol/SConsopts
@@ -48,6 +48,7 @@ all_protocols = [
'MOSI_SMP_directory_1level',
'MSI_MOSI_CMP_directory',
'MOESI_hammer',
+ 'Network_test',
]
opt = EnumVariable('PROTOCOL', 'Coherence protocol for Ruby', 'MI_example',
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
index 3e5e1cbe8..19b4c3d04 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
@@ -38,7 +38,6 @@ BaseGarnetNetwork::BaseGarnetNetwork(const Params *p)
m_vcs_per_class = p->vcs_per_class;
m_buffers_per_data_vc = p->buffers_per_data_vc;
m_buffers_per_ctrl_vc = p->buffers_per_ctrl_vc;
- m_using_network_testing = p->using_network_testing;
}
void
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
index 4a1856e43..d01225232 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
@@ -36,6 +36,7 @@
#ifndef __MEM_RUBY_NETWORK_GARNET_BASEGARNETNETWORK_HH__
#define __MEM_RUBY_NETWORK_GARNET_BASEGARNETNETWORK_HH__
+#include "math.h"
#include "mem/ruby/network/garnet/NetworkHeader.hh"
#include "mem/ruby/network/Network.hh"
#include "params/BaseGarnetNetwork.hh"
@@ -47,7 +48,6 @@ class BaseGarnetNetwork : public Network
BaseGarnetNetwork(const Params *p);
void init();
- bool isNetworkTesting() {return m_using_network_testing; }
int getFlitSize() {return m_flit_size; }
int getNumPipeStages() {return m_number_of_pipe_stages; }
int getVCsPerClass() {return m_vcs_per_class; }
@@ -60,7 +60,6 @@ class BaseGarnetNetwork : public Network
int m_vcs_per_class;
int m_buffers_per_data_vc;
int m_buffers_per_ctrl_vc;
- bool m_using_network_testing;
};
#endif // __MEM_RUBY_NETWORK_GARNET_BASEGARNETNETWORK_HH__
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
index 44b6bd149..3594e93b6 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
@@ -39,4 +39,3 @@ class BaseGarnetNetwork(RubyNetwork):
vcs_per_class = Param.Int(4, "virtual channels per message class");
buffers_per_data_vc = Param.Int(4, "buffers per data virtual channel");
buffers_per_ctrl_vc = Param.Int(1, "buffers per ctrl virtual channel");
- using_network_testing = Param.Bool(False, "network testing enable");
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
index dbfabc8f1..f0b8ccce7 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
@@ -307,15 +307,15 @@ GarnetNetwork_d::printStats(ostream& out) const
}
out << "-------------" << endl;
- // out << "Total flits injected = " << m_flits_injected << endl;
- // out << "Total flits received = " << m_flits_received << endl;
+ out << "Total flits injected = " << m_flits_injected << endl;
+ out << "Total flits received = " << m_flits_received << endl;
out << "Average network latency = "
<< ((double) m_network_latency/ (double) m_flits_received)<< endl;
- // out << "Average queueing latency = "
- // << ((double) m_queueing_latency/ (double) m_flits_received)<< endl;
- // out << "Average latency = "
- // << ((double) (m_queueing_latency + m_network_latency) /
- // (double) m_flits_received)<< endl;
+ out << "Average queueing (at source NI) latency = "
+ << ((double) m_queueing_latency/ (double) m_flits_received)<< endl;
+ out << "Average latency = "
+ << ((double) (m_queueing_latency + m_network_latency) /
+ (double) m_flits_received)<< endl;
out << "-------------" << endl;
double m_total_link_power = 0.0;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
index 8299a294f..14105a38c 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
@@ -241,12 +241,9 @@ NetworkInterface_d::wakeup()
bool free_signal = false;
if (t_flit->get_type() == TAIL_ || t_flit->get_type() == HEAD_TAIL_) {
free_signal = true;
- // When we are doing network only testing, the messages do not
- // have to be buffered into the protocol buffers
- if (!m_net_ptr->isNetworkTesting()) {
- outNode_ptr[t_flit->get_vnet()]->
- enqueue(t_flit->get_msg_ptr(), 1);
- }
+
+ outNode_ptr[t_flit->get_vnet()]->enqueue(
+ t_flit->get_msg_ptr(), 1);
}
// Simply send a credit back since we are not buffering
// this flit in the NI
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
index afc841a1b..60ec09e58 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
@@ -262,12 +262,8 @@ NetworkInterface::wakeup()
DPRINTF(RubyNetwork, "m_id: %d, Message delivered at time: %lld\n",
m_id, g_eventQueue_ptr->getTime());
- // When we are doing network only testing, the messages do not
- // have to be buffered into the message buffers of the protocol
- if (!m_net_ptr->isNetworkTesting()) {
- outNode_ptr[t_flit->get_vnet()]->enqueue(
- t_flit->get_msg_ptr(), 1);
- }
+ outNode_ptr[t_flit->get_vnet()]->enqueue(
+ t_flit->get_msg_ptr(), 1);
// signal the upstream router that this vc can be freed now
inNetLink->release_vc_link(t_flit->get_vc(),
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 6b0f6e49f..a5f1a06fa 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -77,6 +77,8 @@ Sequencer::Sequencer(const Params *p)
assert(m_deadlock_threshold > 0);
assert(m_instCache_ptr != NULL);
assert(m_dataCache_ptr != NULL);
+
+ m_usingNetworkTester = p->using_network_tester;
}
Sequencer::~Sequencer()
@@ -390,7 +392,11 @@ Sequencer::writeCallback(const Address& address,
// For Alpha, properly handle LL, SC, and write requests with respect to
// locked cache blocks.
//
- bool success = handleLlsc(address, request);
+ // Not valid for Network_test protocl
+ //
+ bool success = true;
+ if(!m_usingNetworkTester)
+ success = handleLlsc(address, request);
if (request->ruby_request.type == RubyRequestType_Locked_RMW_Read) {
m_controller->blockOnQueue(address, m_mandatory_q_ptr);
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 14b6997e8..ff3a0d5b1 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -152,6 +152,8 @@ class Sequencer : public RubyPort, public Consumer
int m_load_waiting_on_store_cycles;
int m_load_waiting_on_load_cycles;
+ bool m_usingNetworkTester;
+
class SequencerWakeupEvent : public Event
{
private:
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index f6d847e10..16fb795f8 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -40,6 +40,7 @@ class RubyPort(MemObject):
physmem = Param.PhysicalMemory("")
physMemPort = Port("port to physical memory")
using_ruby_tester = Param.Bool(False, "")
+ using_network_tester = Param.Bool(False, "")
access_phys_mem = Param.Bool(True,
"should the rubyport atomically update phys_mem")
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 02:05:24 +0000