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-rw-r--r--src/mem/dram_ctrl.cc66
-rw-r--r--src/mem/dram_ctrl.hh8
2 files changed, 20 insertions, 54 deletions
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index b5566c88d..1e00dd606 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -1042,47 +1042,6 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
}
void
-DRAMCtrl::moveToRespQ()
-{
- // Remove from read queue
- DRAMPacket* dram_pkt = readQueue.front();
- readQueue.pop_front();
-
- // sanity check
- assert(dram_pkt->size <= burstSize);
-
- // Insert into response queue sorted by readyTime
- // It will be sent back to the requestor at its
- // readyTime
- if (respQueue.empty()) {
- respQueue.push_front(dram_pkt);
- assert(!respondEvent.scheduled());
- assert(dram_pkt->readyTime >= curTick());
- schedule(respondEvent, dram_pkt->readyTime);
- } else {
- bool done = false;
- auto i = respQueue.begin();
- while (!done && i != respQueue.end()) {
- if ((*i)->readyTime > dram_pkt->readyTime) {
- respQueue.insert(i, dram_pkt);
- done = true;
- }
- ++i;
- }
-
- if (!done)
- respQueue.push_back(dram_pkt);
-
- assert(respondEvent.scheduled());
-
- if (respQueue.front()->readyTime < respondEvent.when()) {
- assert(respQueue.front()->readyTime >= curTick());
- reschedule(respondEvent, respQueue.front()->readyTime);
- }
- }
-}
-
-void
DRAMCtrl::processNextReqEvent()
{
if (busState == READ_TO_WRITE) {
@@ -1152,13 +1111,28 @@ DRAMCtrl::processNextReqEvent()
// front of the read queue
chooseNext(readQueue);
- doDRAMAccess(readQueue.front());
+ DRAMPacket* dram_pkt = readQueue.front();
+
+ doDRAMAccess(dram_pkt);
// At this point we're done dealing with the request
- // It will be moved to a separate response queue with a
- // correct readyTime, and eventually be sent back at that
- // time
- moveToRespQ();
+ readQueue.pop_front();
+
+ // sanity check
+ assert(dram_pkt->size <= burstSize);
+ assert(dram_pkt->readyTime >= curTick());
+
+ // Insert into response queue. It will be sent back to the
+ // requestor at its readyTime
+ if (respQueue.empty()) {
+ assert(!respondEvent.scheduled());
+ schedule(respondEvent, dram_pkt->readyTime);
+ } else {
+ assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
+ assert(respondEvent.scheduled());
+ }
+
+ respQueue.push_back(dram_pkt);
// we have so many writes that we have to transition
if (writeQueue.size() > writeHighThreshold) {
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index c673e0595..24f9729c5 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -367,14 +367,6 @@ class DRAMCtrl : public AbstractMemory
void chooseNext(std::deque<DRAMPacket*>& queue);
/**
- * Move the request at the head of the read queue to the response
- * queue, sorting by readyTime.\ If it is the only packet in the
- * response queue, schedule a respond event to send it back to the
- * outside world
- */
- void moveToRespQ();
-
- /**
* For FR-FCFS policy reorder the read/write queue depending on row buffer
* hits and earliest banks available in DRAM
*/