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-rw-r--r--src/mem/bus.cc7
-rw-r--r--src/mem/bus.hh1
-rw-r--r--src/mem/cache/BaseCache.py3
-rw-r--r--src/mem/page_table.cc22
-rw-r--r--src/mem/page_table.hh16
5 files changed, 34 insertions, 15 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index bde90c83f..0c1f384b1 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -607,6 +607,13 @@ Bus::drain(Event * de)
}
}
+void
+Bus::startup()
+{
+ if (tickNextIdle < curTick)
+ tickNextIdle = (curTick / clock) * clock + clock;
+}
+
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
Param<int> bus_id;
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 33619bf45..bd51337ed 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -264,6 +264,7 @@ class Bus : public MemObject
virtual void deletePortRefs(Port *p);
virtual void init();
+ virtual void startup();
unsigned int drain(Event *de);
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 4b98f6b30..32f3f0174 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -27,6 +27,7 @@
# Authors: Nathan Binkert
from m5.params import *
+from m5.proxy import Self
from MemObject import MemObject
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
@@ -77,7 +78,7 @@ class BaseCache(MemObject):
"Squash prefetches with a later time on a subsequent miss")
prefetch_degree = Param.Int(1,
"Degree of the prefetch depth")
- prefetch_latency = Param.Tick(10,
+ prefetch_latency = Param.Latency(10 * Self.latency,
"Latency of the prefetcher")
prefetch_policy = Param.Prefetch('none',
"Type of prefetcher to use")
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 96bc23793..b29a07078 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -90,8 +90,6 @@ PageTable::page_check(Addr addr, int64_t size) const
}
-
-
void
PageTable::allocate(Addr vaddr, int64_t size)
{
@@ -109,12 +107,7 @@ PageTable::allocate(Addr vaddr, int64_t size)
}
pTable[vaddr] = system->new_page();
- pTableCache[2].paddr = pTableCache[1].paddr;
- pTableCache[2].vaddr = pTableCache[1].vaddr;
- pTableCache[1].paddr = pTableCache[0].paddr;
- pTableCache[1].vaddr = pTableCache[0].vaddr;
- pTableCache[0].paddr = pTable[vaddr];
- pTableCache[0].vaddr = vaddr;
+ updateCache(vaddr, pTable[vaddr]);
}
}
@@ -126,16 +119,16 @@ PageTable::translate(Addr vaddr, Addr &paddr)
Addr page_addr = pageAlign(vaddr);
paddr = 0;
- if (pTableCache[0].vaddr == vaddr) {
- paddr = pTableCache[0].paddr;
+ if (pTableCache[0].vaddr == page_addr) {
+ paddr = pTableCache[0].paddr + pageOffset(vaddr);
return true;
}
- if (pTableCache[1].vaddr == vaddr) {
- paddr = pTableCache[1].paddr;
+ if (pTableCache[1].vaddr == page_addr) {
+ paddr = pTableCache[1].paddr + pageOffset(vaddr);
return true;
}
- if (pTableCache[2].vaddr == vaddr) {
- paddr = pTableCache[2].paddr;
+ if (pTableCache[2].vaddr == page_addr) {
+ paddr = pTableCache[2].paddr + pageOffset(vaddr);
return true;
}
@@ -145,6 +138,7 @@ PageTable::translate(Addr vaddr, Addr &paddr)
return false;
}
+ updateCache(page_addr, iter->second);
paddr = iter->second + pageOffset(vaddr);
return true;
}
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 0e2b1f58c..64c824238 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -95,6 +95,22 @@ class PageTable
*/
Fault translate(RequestPtr &req);
+ /**
+ * Update the page table cache.
+ * @param vaddr virtual address (page aligned) to check
+ * @param paddr physical address (page aligned) to return
+ */
+ inline void updateCache(Addr vaddr, Addr paddr)
+ {
+ pTableCache[2].paddr = pTableCache[1].paddr;
+ pTableCache[2].vaddr = pTableCache[1].vaddr;
+ pTableCache[1].paddr = pTableCache[0].paddr;
+ pTableCache[1].vaddr = pTableCache[0].vaddr;
+ pTableCache[0].paddr = paddr;
+ pTableCache[0].vaddr = vaddr;
+ }
+
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};