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-rw-r--r--src/mem/cache/blk.hh8
-rw-r--r--src/mem/cache/prefetch/base.cc4
-rw-r--r--src/mem/cache/prefetch/ghb.cc14
-rw-r--r--src/mem/cache/prefetch/ghb.hh4
-rw-r--r--src/mem/cache/prefetch/stride.cc10
-rw-r--r--src/mem/cache/prefetch/stride.hh4
-rw-r--r--src/mem/physical.cc16
-rw-r--r--src/mem/physical.hh9
-rw-r--r--src/mem/request.hh36
9 files changed, 50 insertions, 55 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 9bfbd646d..bdf323d87 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -108,18 +108,16 @@ class CacheBlk
*/
class Lock {
public:
- int cpuNum; // locking CPU
- int threadNum; // locking thread ID within CPU
+ int contextId; // locking context
// check for matching execution context
bool matchesContext(Request *req)
{
- return (cpuNum == req->getCpuNum() &&
- threadNum == req->getThreadNum());
+ return (contextId == req->contextId());
}
Lock(Request *req)
- : cpuNum(req->getCpuNum()), threadNum(req->getThreadNum())
+ : contextId(req->contextId())
{
}
};
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index fcc02ff28..a7e6cfdfc 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -203,8 +203,8 @@ BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time)
PacketPtr prefetch;
prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, -1);
prefetch->allocate();
- prefetch->req->setThreadContext(pkt->req->getCpuNum(),
- pkt->req->getThreadNum());
+ prefetch->req->setThreadContext(pkt->req->contextId(),
+ pkt->req->threadId());
prefetch->time = time + (*delay); //@todo ADD LATENCY HERE
//... initialize
diff --git a/src/mem/cache/prefetch/ghb.cc b/src/mem/cache/prefetch/ghb.cc
index f5b88e1a6..c8b87e99d 100644
--- a/src/mem/cache/prefetch/ghb.cc
+++ b/src/mem/cache/prefetch/ghb.cc
@@ -42,16 +42,16 @@ GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
- int cpuID = pkt->req->getCpuNum();
- if (!useCPUId) cpuID = 0;
+ int contextId = pkt->req->contextId();
+ if (!useContextId) contextId = 0;
- int new_stride = blkAddr - last_miss_addr[cpuID];
- int old_stride = last_miss_addr[cpuID] -
- second_last_miss_addr[cpuID];
+ int new_stride = blkAddr - last_miss_addr[contextId];
+ int old_stride = last_miss_addr[contextId] -
+ second_last_miss_addr[contextId];
- second_last_miss_addr[cpuID] = last_miss_addr[cpuID];
- last_miss_addr[cpuID] = blkAddr;
+ second_last_miss_addr[contextId] = last_miss_addr[contextId];
+ last_miss_addr[contextId] = blkAddr;
if (new_stride == old_stride) {
for (int d=1; d <= degree; d++) {
diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh
index 4fb692016..156a74afa 100644
--- a/src/mem/cache/prefetch/ghb.hh
+++ b/src/mem/cache/prefetch/ghb.hh
@@ -47,13 +47,13 @@ class GHBPrefetcher : public BasePrefetcher
Tick latency;
int degree;
- bool useCPUId;
+ bool useContextId;
public:
GHBPrefetcher(const BaseCacheParams *p)
: BasePrefetcher(p), latency(p->prefetch_latency),
- degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
+ degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id)
{
}
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index e93058d6e..ad5846daa 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -41,18 +41,18 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
- int cpuID = pkt->req->getCpuNum();
- if (!useCPUId) cpuID = 0;
+ int contextId = pkt->req->contextId();
+ if (!useContextId) contextId = 0;
/* Scan Table for IAddr Match */
/* std::list<strideEntry*>::iterator iter;
- for (iter=table[cpuID].begin();
- iter !=table[cpuID].end();
+ for (iter=table[contextId].begin();
+ iter !=table[contextId].end();
iter++) {
if ((*iter)->IAddr == pkt->pc) break;
}
- if (iter != table[cpuID].end()) {
+ if (iter != table[contextId].end()) {
//Hit in table
int newStride = blkAddr - (*iter)->MAddr;
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index ca173277c..4738fd9bc 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -63,14 +63,14 @@ class StridePrefetcher : public BasePrefetcher
std::list<strideEntry*> table[64/*MAX_CPUS*/];
Tick latency;
int degree;
- bool useCPUId;
+ bool useContextId;
public:
StridePrefetcher(const BaseCacheParams *p)
: BasePrefetcher(p), latency(p->prefetch_latency),
- degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
+ degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id)
{
}
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 20e19669c..16ff3de6d 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -139,16 +139,16 @@ PhysicalMemory::trackLoadLocked(PacketPtr pkt)
for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
if (i->matchesContext(req)) {
- DPRINTF(LLSC, "Modifying lock record: cpu %d thread %d addr %#x\n",
- req->getCpuNum(), req->getThreadNum(), paddr);
+ DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
+ req->contextId(), paddr);
i->addr = paddr;
return;
}
}
// no record for this xc: need to allocate a new one
- DPRINTF(LLSC, "Adding lock record: cpu %d thread %d addr %#x\n",
- req->getCpuNum(), req->getThreadNum(), paddr);
+ DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
+ req->contextId(), paddr);
lockedAddrList.push_front(LockedAddr(req));
}
@@ -183,14 +183,14 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
// it's a store conditional, and as far as the memory
// system can tell, the requesting context's lock is
// still valid.
- DPRINTF(LLSC, "StCond success: cpu %d thread %d addr %#x\n",
- req->getCpuNum(), req->getThreadNum(), paddr);
+ DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
+ req->contextId(), paddr);
success = true;
}
// Get rid of our record of this lock and advance to next
- DPRINTF(LLSC, "Erasing lock record: cpu %d thread %d addr %#x\n",
- i->cpuNum, i->threadNum, paddr);
+ DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
+ i->contextId, paddr);
i = lockedAddrList.erase(i);
}
else {
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 2a0086ba9..d18138ecd 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -90,20 +90,17 @@ class PhysicalMemory : public MemObject
static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
Addr addr; // locked address
- int cpuNum; // locking CPU
- int threadNum; // locking thread ID within CPU
+ int contextId; // locking hw context
// check for matching execution context
bool matchesContext(Request *req)
{
- return (cpuNum == req->getCpuNum() &&
- threadNum == req->getThreadNum());
+ return (contextId == req->contextId());
}
LockedAddr(Request *req)
: addr(mask(req->getPaddr())),
- cpuNum(req->getCpuNum()),
- threadNum(req->getThreadNum())
+ contextId(req->contextId())
{
}
};
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 613655ea4..da0d9c7e0 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -115,10 +115,10 @@ class Request : public FastAlloc
* store conditional or the compare value for a CAS. */
uint64_t extraData;
- /** The cpu number (for statistics, typically). */
- int cpuNum;
- /** The requesting thread id (for statistics, typically). */
- int threadNum;
+ /** The context ID (for statistics, typically). */
+ int _contextId;
+ /** The thread ID (id within this CPU) */
+ int _threadId;
/** program counter of initiating access; for tracing/debugging */
Addr pc;
@@ -129,8 +129,8 @@ class Request : public FastAlloc
bool validAsidVaddr;
/** Whether or not the sc result is valid. */
bool validExData;
- /** Whether or not the cpu number & thread ID are valid. */
- bool validCpuAndThreadNums;
+ /** Whether or not the context ID is valid. */
+ bool validContextAndThreadIds;
/** Whether or not the pc is valid. */
bool validPC;
@@ -138,7 +138,7 @@ class Request : public FastAlloc
/** Minimal constructor. No fields are initialized. */
Request()
: validPaddr(false), validAsidVaddr(false),
- validExData(false), validCpuAndThreadNums(false), validPC(false)
+ validExData(false), validContextAndThreadIds(false), validPC(false)
{}
/**
@@ -146,13 +146,13 @@ class Request : public FastAlloc
* just physical address, size, flags, and timestamp (to curTick).
* These fields are adequate to perform a request. */
Request(Addr _paddr, int _size, int _flags)
- : validCpuAndThreadNums(false)
+ : validContextAndThreadIds(false)
{ setPhys(_paddr, _size, _flags); }
Request(int _asid, Addr _vaddr, int _size, int _flags, Addr _pc,
- int _cpuNum, int _threadNum)
+ int _context_id, int _thread_id)
{
- setThreadContext(_cpuNum, _threadNum);
+ setThreadContext(_context_id, _thread_id);
setVirt(_asid, _vaddr, _size, _flags, _pc);
}
@@ -160,11 +160,11 @@ class Request : public FastAlloc
/**
* Set up CPU and thread numbers. */
- void setThreadContext(int _cpuNum, int _threadNum)
+ void setThreadContext(int _context_id, int _thread_id)
{
- cpuNum = _cpuNum;
- threadNum = _threadNum;
- validCpuAndThreadNums = true;
+ _contextId = _context_id;
+ _threadId = _thread_id;
+ validContextAndThreadIds = true;
}
/**
@@ -261,10 +261,10 @@ class Request : public FastAlloc
void setExtraData(uint64_t _extraData)
{ extraData = _extraData; validExData = true; }
- /** Accessor function for cpu number.*/
- int getCpuNum() { assert(validCpuAndThreadNums); return cpuNum; }
- /** Accessor function for thread number.*/
- int getThreadNum() { assert(validCpuAndThreadNums); return threadNum; }
+ /** Accessor function for context ID.*/
+ int contextId() { assert(validContextAndThreadIds); return _contextId; }
+ /** Accessor function for thread ID. */
+ int threadId() { assert(validContextAndThreadIds); return _threadId; }
/** Accessor function for pc.*/
Addr getPC() { assert(validPC); return pc; }
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 20:11:36 +0000