diff options
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/SConscript | 9 | ||||
-rw-r--r-- | src/mem/cache/base.cc | 13 | ||||
-rw-r--r-- | src/mem/cache/base.hh | 10 | ||||
-rw-r--r-- | src/mem/page_table.cc | 7 | ||||
-rw-r--r-- | src/mem/physical.cc | 1 | ||||
-rw-r--r-- | src/mem/translating_port.cc | 31 | ||||
-rw-r--r-- | src/mem/translating_port.hh | 3 | ||||
-rw-r--r-- | src/mem/vport.hh | 1 |
8 files changed, 29 insertions, 46 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 50423fa67..8418a4f51 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -37,20 +37,17 @@ SimObject('MemObject.py') Source('bridge.cc') Source('bus.cc') Source('mem_object.cc') +Source('mport.cc') Source('packet.cc') Source('port.cc') Source('tport.cc') -Source('mport.cc') +Source('vport.cc') if env['TARGET_ISA'] != 'no': SimObject('PhysicalMemory.py') Source('dram.cc') - Source('physical.cc') - -if env['FULL_SYSTEM']: - Source('vport.cc') -elif env['TARGET_ISA'] != 'no': Source('page_table.cc') + Source('physical.cc') Source('translating_port.cc') DebugFlag('Bus') diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 7863edde0..09e3d0869 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -38,6 +38,7 @@ #include "debug/Cache.hh" #include "mem/cache/base.hh" #include "mem/cache/mshr.hh" +#include "sim/full_system.hh" using namespace std; @@ -151,11 +152,7 @@ BaseCache::regStats() const string &cstr = cmd.toString(); hits[access_idx] -#if FULL_SYSTEM - .init(_numCpus + 1) -#else - .init(_numCpus) -#endif + .init(FullSystem ? (_numCpus + 1) : _numCpus) .name(name() + "." + cstr + "_hits") .desc("number of " + cstr + " hits") .flags(total | nozero | nonan) @@ -192,11 +189,7 @@ BaseCache::regStats() const string &cstr = cmd.toString(); misses[access_idx] -#if FULL_SYSTEM - .init(_numCpus + 1) -#else - .init(_numCpus) -#endif + .init(FullSystem ? (_numCpus + 1) : _numCpus) .name(name() + "." + cstr + "_misses") .desc("number of " + cstr + " misses") .flags(total | nozero | nonan) diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 297692b32..8c39a2400 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -47,7 +47,6 @@ #include "base/statistics.hh" #include "base/trace.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "debug/Cache.hh" #include "debug/CachePort.hh" #include "mem/cache/mshr_queue.hh" @@ -57,6 +56,7 @@ #include "mem/tport.hh" #include "params/BaseCache.hh" #include "sim/eventq.hh" +#include "sim/full_system.hh" #include "sim/sim_exit.hh" class MSHR; @@ -505,12 +505,10 @@ class BaseCache : public MemObject * available, meanwhile writeback hit/miss stats are not used * in any aggregate hit/miss calculations, so just lump them all * in bucket 0 */ -#if FULL_SYSTEM - } else if (id == -1) { + } else if (FullSystem && id == -1) { // Device accesses have id -1 // lump device accesses into their own bucket misses[pkt->cmdToIndex()][_numCpus]++; -#endif } else { misses[pkt->cmdToIndex()][id % _numCpus]++; } @@ -533,12 +531,10 @@ class BaseCache : public MemObject if (pkt->cmd == MemCmd::Writeback) { assert(id == -1); hits[pkt->cmdToIndex()][0]++; -#if FULL_SYSTEM - } else if (id == -1) { + } else if (FullSystem && id == -1) { // Device accesses have id -1 // lump device accesses into their own bucket hits[pkt->cmdToIndex()][_numCpus]++; -#endif } else { /* the % is necessary in case there are switch cpus */ hits[pkt->cmdToIndex()][id % _numCpus]++; diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index ce3448c4c..f47e73c74 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -217,12 +217,13 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) { int i = 0, count; paramIn(cp, section, "ptable.size", count); - Addr vaddr; - TheISA::TlbEntry *entry; pTable.clear(); - while(i < count) { + while (i < count) { + TheISA::TlbEntry *entry; + Addr vaddr; + paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); entry = new TheISA::TlbEntry(); entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 91b9052a1..d5c4e892f 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -59,7 +59,6 @@ #include "base/misc.hh" #include "base/random.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" #include "debug/LLSC.hh" #include "debug/MemoryAccess.hh" diff --git a/src/mem/translating_port.cc b/src/mem/translating_port.cc index 3ea728349..7d3123012 100644 --- a/src/mem/translating_port.cc +++ b/src/mem/translating_port.cc @@ -31,6 +31,7 @@ #include <string> +#include "arch/isa_traits.hh" #include "base/chunk_generator.hh" #include "config/the_isa.hh" #include "mem/page_table.hh" @@ -40,10 +41,9 @@ using namespace TheISA; -TranslatingPort::TranslatingPort(const std::string &_name, - Process *p, AllocType alloc) - : FunctionalPort(_name), pTable(p->pTable), process(p), - allocating(alloc) +TranslatingPort::TranslatingPort(const std::string &_name, Process *p, + AllocType alloc) + : FunctionalPort(_name), pTable(p->pTable), process(p), allocating(alloc) { } TranslatingPort::~TranslatingPort() @@ -52,10 +52,10 @@ TranslatingPort::~TranslatingPort() bool TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size) { - Addr paddr; int prevSize = 0; for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { + Addr paddr; if (!pTable->translate(gen.addr(),paddr)) return false; @@ -78,11 +78,10 @@ TranslatingPort::readBlob(Addr addr, uint8_t *p, int size) bool TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) { - - Addr paddr; int prevSize = 0; for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { + Addr paddr; if (!pTable->translate(gen.addr(), paddr)) { if (allocating == Always) { @@ -117,9 +116,8 @@ TranslatingPort::writeBlob(Addr addr, uint8_t *p, int size) bool TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) { - Addr paddr; - for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { + Addr paddr; if (!pTable->translate(gen.addr(), paddr)) { if (allocating == Always) { @@ -130,7 +128,6 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) return false; } } - Port::memsetBlob(paddr, val, gen.size()); } @@ -148,14 +145,15 @@ TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size) bool TranslatingPort::tryWriteString(Addr addr, const char *str) { - Addr paddr,vaddr; uint8_t c; - vaddr = addr; + Addr vaddr = addr; do { c = *str++; - if (!pTable->translate(vaddr++,paddr)) + Addr paddr; + + if (!pTable->translate(vaddr++, paddr)) return false; Port::writeBlob(paddr, &c, 1); @@ -174,13 +172,14 @@ TranslatingPort::writeString(Addr addr, const char *str) bool TranslatingPort::tryReadString(std::string &str, Addr addr) { - Addr paddr,vaddr; uint8_t c; - vaddr = addr; + Addr vaddr = addr; do { - if (!pTable->translate(vaddr++,paddr)) + Addr paddr; + + if (!pTable->translate(vaddr++, paddr)) return false; Port::readBlob(paddr, &c, 1); diff --git a/src/mem/translating_port.hh b/src/mem/translating_port.hh index 76c7947be..438d8fe61 100644 --- a/src/mem/translating_port.hh +++ b/src/mem/translating_port.hh @@ -52,8 +52,7 @@ class TranslatingPort : public FunctionalPort AllocType allocating; public: - TranslatingPort(const std::string &_name, - Process *p, AllocType alloc); + TranslatingPort(const std::string &_name, Process *p, AllocType alloc); virtual ~TranslatingPort(); bool tryReadBlob(Addr addr, uint8_t *p, int size); diff --git a/src/mem/vport.hh b/src/mem/vport.hh index 1dfc0ea23..7cf24587c 100644 --- a/src/mem/vport.hh +++ b/src/mem/vport.hh @@ -39,7 +39,6 @@ #define __MEM_VPORT_HH__ #include "arch/vtophys.hh" -#include "config/full_system.hh" #include "mem/port_impl.hh" /** A class that translates a virtual address to a physical address and then |