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-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index b4576f87e..f737707bd 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -278,8 +278,7 @@ AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
Cycles latency,
const DataBlock &block, int size)
{
- RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
- m_masterId);
+ RequestPtr req = new Request(addr, size, 0, m_masterId);
PacketPtr pkt = Packet::createWrite(req);
uint8_t *newData = new uint8_t[size];