summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/cache/base.hh12
-rw-r--r--src/mem/cache/cache.hh24
-rw-r--r--src/mem/cache/cache_impl.hh4
3 files changed, 20 insertions, 20 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index b9b42da78..dce40e915 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -262,12 +262,12 @@ class BaseCache : public MemObject
const int numTarget;
/** Do we forward snoops from mem side port through to cpu side port? */
- bool forwardSnoops;
+ const bool forwardSnoops;
/** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
* never try to forward ownership and similar optimizations to the cpu
* side */
- bool isTopLevel;
+ const bool isTopLevel;
/**
* Bit vector of the blocking reasons for the access path.
@@ -290,7 +290,7 @@ class BaseCache : public MemObject
/**
* The address range to which the cache responds on the CPU side.
* Normally this is all possible memory addresses. */
- AddrRangeList addrRanges;
+ const AddrRangeList addrRanges;
public:
/** System we are currently operating in. */
@@ -495,7 +495,7 @@ class BaseCache : public MemObject
/**
* Returns true if the cache is blocked for accesses.
*/
- bool isBlocked()
+ bool isBlocked() const
{
return blocked != 0;
}
@@ -560,9 +560,9 @@ class BaseCache : public MemObject
virtual unsigned int drain(DrainManager *dm);
- virtual bool inCache(Addr addr) = 0;
+ virtual bool inCache(Addr addr) const = 0;
- virtual bool inMissQueue(Addr addr) = 0;
+ virtual bool inMissQueue(Addr addr) const = 0;
void incMissCount(PacketPtr pkt)
{
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 6b062ef40..5cd6bf961 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -290,12 +290,6 @@ class Cache : public BaseCache
*/
void uncacheableFlush(PacketPtr pkt);
- public:
- /** Instantiates a basic cache object. */
- Cache(const Params *p, TagStore *tags);
-
- void regStats();
-
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
@@ -356,7 +350,7 @@ class Cache : public BaseCache
* current request in cpu_pkt should just be forwarded on.
*/
PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
- bool needsExclusive);
+ bool needsExclusive) const;
/**
* Return the next MSHR to service, either a pending miss from the
@@ -389,22 +383,28 @@ class Cache : public BaseCache
return mshrQueue.allocated != 0;
}
- CacheBlk *findBlock(Addr addr) {
+ CacheBlk *findBlock(Addr addr) const {
return tags->findBlock(addr);
}
- bool inCache(Addr addr) {
+ bool inCache(Addr addr) const {
return (tags->findBlock(addr) != 0);
}
- bool inMissQueue(Addr addr) {
+ bool inMissQueue(Addr addr) const {
return (mshrQueue.findMatch(addr) != 0);
}
/**
* Find next request ready time from among possible sources.
*/
- Tick nextMSHRReadyTime();
+ Tick nextMSHRReadyTime() const;
+
+ public:
+ /** Instantiates a basic cache object. */
+ Cache(const Params *p, TagStore *tags);
+
+ void regStats();
/** serialize the state of the caches
* We currently don't support checkpointing cache state, so this panics.
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 21c8e16d6..a5f1b4844 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -586,7 +586,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
template<class TagStore>
PacketPtr
Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
- bool needsExclusive)
+ bool needsExclusive) const
{
bool blkValid = blk && blk->isValid();
@@ -1645,7 +1645,7 @@ Cache<TagStore>::getTimingPacket()
template<class TagStore>
Tick
-Cache<TagStore>::nextMSHRReadyTime()
+Cache<TagStore>::nextMSHRReadyTime() const
{
Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(),
writeBuffer.nextMSHRReadyTime());