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-rw-r--r--src/mem/protocol/RubySlicc_Util.sm3
-rw-r--r--src/mem/ruby/SConscript1
-rw-r--r--src/mem/ruby/common/BoolVec.cc50
-rw-r--r--src/mem/ruby/common/BoolVec.hh45
-rw-r--r--src/mem/ruby/common/SConscript1
-rw-r--r--src/mem/ruby/slicc_interface/RubySlicc_Util.hh13
6 files changed, 113 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/protocol/RubySlicc_Util.sm
index 9e78be65f..a179e5bbc 100644
--- a/src/mem/protocol/RubySlicc_Util.sm
+++ b/src/mem/protocol/RubySlicc_Util.sm
@@ -43,3 +43,6 @@ Addr setOffset(Addr addr, int offset);
Addr makeLineAddress(Addr addr);
int getOffset(Addr addr);
int mod(int val, int mod);
+structure(BoolVec, external="yes") {
+}
+int countBoolVec(BoolVec bVec);
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 2ab9c024f..fbbc5686e 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -115,6 +115,7 @@ MakeInclude('slicc_interface/RubyRequest.hh')
# External types
MakeInclude('common/Address.hh')
+MakeInclude('common/BoolVec.hh')
MakeInclude('common/DataBlock.hh')
MakeInclude('common/MachineID.hh')
MakeInclude('common/NetDest.hh')
diff --git a/src/mem/ruby/common/BoolVec.cc b/src/mem/ruby/common/BoolVec.cc
new file mode 100644
index 000000000..34a8fe057
--- /dev/null
+++ b/src/mem/ruby/common/BoolVec.cc
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Brad Beckmann
+ */
+
+#include "mem/ruby/common/BoolVec.hh"
+
+#include <iostream>
+#include <vector>
+
+std::ostream& operator<<(std::ostream& os, const BoolVec& myvector) {
+ for (const auto& it: myvector) {
+ os << " " << it;
+ }
+ return os;
+}
diff --git a/src/mem/ruby/common/BoolVec.hh b/src/mem/ruby/common/BoolVec.hh
new file mode 100644
index 000000000..0323ecc1e
--- /dev/null
+++ b/src/mem/ruby/common/BoolVec.hh
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Brad Beckmann
+ */
+
+#include <ostream>
+#include <vector>
+
+typedef std::vector<bool> BoolVec;
+
+std::ostream& operator<<(std::ostream& os, const std::vector<bool>& myvector);
diff --git a/src/mem/ruby/common/SConscript b/src/mem/ruby/common/SConscript
index f8660da39..6a53fb7c8 100644
--- a/src/mem/ruby/common/SConscript
+++ b/src/mem/ruby/common/SConscript
@@ -34,6 +34,7 @@ if env['PROTOCOL'] == 'None':
Return()
Source('Address.cc')
+Source('BoolVec.cc')
Source('Consumer.cc')
Source('DataBlock.cc')
Source('Histogram.cc')
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 61813bb30..4a48d3efe 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -38,6 +38,7 @@
#include "debug/RubySlicc.hh"
#include "mem/packet.hh"
#include "mem/ruby/common/Address.hh"
+#include "mem/ruby/common/BoolVec.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
@@ -125,4 +126,16 @@ testAndWrite(Addr addr, DataBlock& blk, Packet *pkt)
return false;
}
+inline int
+countBoolVec(BoolVec bVec)
+{
+ int count = 0;
+ for (const auto &it: bVec) {
+ if (it) {
+ count++;
+ }
+ }
+ return count;
+}
+
#endif // __MEM_RUBY_SLICC_INTERFACE_RUBYSLICCUTIL_HH__