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-rw-r--r--src/mem/SConscript11
-rw-r--r--src/mem/cache/base.cc13
-rw-r--r--src/mem/cache/base.hh10
-rw-r--r--src/mem/page_table.cc7
-rw-r--r--src/mem/physical.cc1
-rw-r--r--src/mem/se_translating_port_proxy.cc23
6 files changed, 26 insertions, 39 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index dafc8c4a2..09cc93c77 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -37,21 +37,18 @@ SimObject('MemObject.py')
Source('bridge.cc')
Source('bus.cc')
Source('mem_object.cc')
+Source('mport.cc')
Source('packet.cc')
Source('port.cc')
Source('tport.cc')
-Source('mport.cc')
+Source('fs_translating_port_proxy.cc')
+Source('se_translating_port_proxy.cc')
if env['TARGET_ISA'] != 'no':
SimObject('PhysicalMemory.py')
Source('dram.cc')
- Source('physical.cc')
-
-if env['FULL_SYSTEM']:
- Source('fs_translating_port_proxy.cc')
-elif env['TARGET_ISA'] != 'no':
Source('page_table.cc')
- Source('se_translating_port_proxy.cc')
+ Source('physical.cc')
DebugFlag('Bus')
DebugFlag('BusAddrRanges')
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 278329152..2b7fa4b9f 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -38,6 +38,7 @@
#include "debug/Cache.hh"
#include "mem/cache/base.hh"
#include "mem/cache/mshr.hh"
+#include "sim/full_system.hh"
using namespace std;
@@ -149,11 +150,7 @@ BaseCache::regStats()
const string &cstr = cmd.toString();
hits[access_idx]
-#if FULL_SYSTEM
- .init(_numCpus + 1)
-#else
- .init(_numCpus)
-#endif
+ .init(FullSystem ? (_numCpus + 1) : _numCpus)
.name(name() + "." + cstr + "_hits")
.desc("number of " + cstr + " hits")
.flags(total | nozero | nonan)
@@ -190,11 +187,7 @@ BaseCache::regStats()
const string &cstr = cmd.toString();
misses[access_idx]
-#if FULL_SYSTEM
- .init(_numCpus + 1)
-#else
- .init(_numCpus)
-#endif
+ .init(FullSystem ? (_numCpus + 1) : _numCpus)
.name(name() + "." + cstr + "_misses")
.desc("number of " + cstr + " misses")
.flags(total | nozero | nonan)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e6a5c284f..fded6fca6 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -47,7 +47,6 @@
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
#include "mem/cache/mshr_queue.hh"
@@ -57,6 +56,7 @@
#include "mem/tport.hh"
#include "params/BaseCache.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/sim_exit.hh"
class MSHR;
@@ -505,12 +505,10 @@ class BaseCache : public MemObject
* available, meanwhile writeback hit/miss stats are not used
* in any aggregate hit/miss calculations, so just lump them all
* in bucket 0 */
-#if FULL_SYSTEM
- } else if (id == -1) {
+ } else if (FullSystem && id == -1) {
// Device accesses have id -1
// lump device accesses into their own bucket
misses[pkt->cmdToIndex()][_numCpus]++;
-#endif
} else {
misses[pkt->cmdToIndex()][id % _numCpus]++;
}
@@ -533,12 +531,10 @@ class BaseCache : public MemObject
if (pkt->cmd == MemCmd::Writeback) {
assert(id == -1);
hits[pkt->cmdToIndex()][0]++;
-#if FULL_SYSTEM
- } else if (id == -1) {
+ } else if (FullSystem && id == -1) {
// Device accesses have id -1
// lump device accesses into their own bucket
hits[pkt->cmdToIndex()][_numCpus]++;
-#endif
} else {
/* the % is necessary in case there are switch cpus */
hits[pkt->cmdToIndex()][id % _numCpus]++;
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index ce3448c4c..f47e73c74 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -217,12 +217,13 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
{
int i = 0, count;
paramIn(cp, section, "ptable.size", count);
- Addr vaddr;
- TheISA::TlbEntry *entry;
pTable.clear();
- while(i < count) {
+ while (i < count) {
+ TheISA::TlbEntry *entry;
+ Addr vaddr;
+
paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
entry = new TheISA::TlbEntry();
entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index a63f6e619..09ed8b292 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -59,7 +59,6 @@
#include "base/misc.hh"
#include "base/random.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
diff --git a/src/mem/se_translating_port_proxy.cc b/src/mem/se_translating_port_proxy.cc
index 027930287..0f7ecb491 100644
--- a/src/mem/se_translating_port_proxy.cc
+++ b/src/mem/se_translating_port_proxy.cc
@@ -44,6 +44,7 @@
#include <string>
+#include "arch/isa_traits.hh"
#include "base/chunk_generator.hh"
#include "config/the_isa.hh"
#include "mem/page_table.hh"
@@ -64,10 +65,10 @@ SETranslatingPortProxy::~SETranslatingPortProxy()
bool
SETranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size)
{
- Addr paddr;
int prevSize = 0;
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+ Addr paddr;
if (!pTable->translate(gen.addr(),paddr))
return false;
@@ -90,11 +91,10 @@ SETranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size)
bool
SETranslatingPortProxy::tryWriteBlob(Addr addr, uint8_t *p, int size)
{
-
- Addr paddr;
int prevSize = 0;
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+ Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
@@ -129,9 +129,8 @@ SETranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size)
bool
SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size)
{
- Addr paddr;
-
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+ Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
@@ -160,14 +159,15 @@ SETranslatingPortProxy::memsetBlob(Addr addr, uint8_t val, int size)
bool
SETranslatingPortProxy::tryWriteString(Addr addr, const char *str)
{
- Addr paddr,vaddr;
uint8_t c;
- vaddr = addr;
+ Addr vaddr = addr;
do {
c = *str++;
- if (!pTable->translate(vaddr++,paddr))
+ Addr paddr;
+
+ if (!pTable->translate(vaddr++, paddr))
return false;
PortProxy::writeBlob(paddr, &c, 1);
@@ -186,13 +186,14 @@ SETranslatingPortProxy::writeString(Addr addr, const char *str)
bool
SETranslatingPortProxy::tryReadString(std::string &str, Addr addr)
{
- Addr paddr,vaddr;
uint8_t c;
- vaddr = addr;
+ Addr vaddr = addr;
do {
- if (!pTable->translate(vaddr++,paddr))
+ Addr paddr;
+
+ if (!pTable->translate(vaddr++, paddr))
return false;
PortProxy::readBlob(paddr, &c, 1);
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 02:14:43 +0000