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-rw-r--r--src/mem/ruby/buffers/MessageBuffer.cc6
-rw-r--r--src/mem/ruby/buffers/MessageBuffer.hh4
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh2
-rw-r--r--src/mem/ruby/slicc_interface/Controller.py3
4 files changed, 8 insertions, 7 deletions
diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc
index 0a7a78e8d..0486f627e 100644
--- a/src/mem/ruby/buffers/MessageBuffer.cc
+++ b/src/mem/ruby/buffers/MessageBuffer.cc
@@ -49,7 +49,7 @@ MessageBuffer::MessageBuffer(const string &name)
m_ordering_set = false;
m_strict_fifo = true;
- m_max_size = -1;
+ m_max_size = 0;
m_randomization = true;
m_size_last_time_size_checked = 0;
m_size_at_cycle_start = 0;
@@ -63,7 +63,7 @@ MessageBuffer::MessageBuffer(const string &name)
m_vnet_id = 0;
}
-int
+unsigned int
MessageBuffer::getSize()
{
if (m_time_last_time_size_checked != m_receiver->curCycle()) {
@@ -79,7 +79,7 @@ MessageBuffer::areNSlotsAvailable(unsigned int n)
{
// fast path when message buffers have infinite size
- if (m_max_size == -1) {
+ if (m_max_size == 0) {
return true;
}
diff --git a/src/mem/ruby/buffers/MessageBuffer.hh b/src/mem/ruby/buffers/MessageBuffer.hh
index b65717e2d..444a7fc30 100644
--- a/src/mem/ruby/buffers/MessageBuffer.hh
+++ b/src/mem/ruby/buffers/MessageBuffer.hh
@@ -134,8 +134,8 @@ class MessageBuffer
m_ordering_set = true;
}
- void resize(int size) { m_max_size = size; }
- int getSize();
+ void resize(unsigned int size) { m_max_size = size; }
+ unsigned int getSize();
void setRandomization(bool random_flag) { m_randomization = random_flag; }
void clear();
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index d6ba928fd..4ef3f328b 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -146,7 +146,7 @@ class AbstractController : public ClockedObject, public Consumer
unsigned int m_cur_in_port;
int m_number_of_TBEs;
int m_transitions_per_cycle;
- int m_buffer_size;
+ unsigned int m_buffer_size;
Cycles m_recycle_latency;
//! Map from physical network number to the Message Buffer.
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index 638d50b61..f82e0a70d 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -40,7 +40,8 @@ class RubyController(ClockedObject):
transitions_per_cycle = \
Param.Int(32, "no. of SLICC state machine transitions per cycle")
- buffer_size = Param.Int(0, "max buffer size 0 means infinite")
+ buffer_size = Param.UInt32(0, "max buffer size 0 means infinite")
+
recycle_latency = Param.Cycles(10, "")
number_of_TBEs = Param.Int(256, "")
ruby_system = Param.RubySystem("")