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-rw-r--r--src/mem/abstract_mem.cc12
-rw-r--r--src/mem/abstract_mem.hh2
-rw-r--r--src/mem/addr_mapper.cc15
-rw-r--r--src/mem/bus.cc20
-rw-r--r--src/mem/bus.hh6
-rw-r--r--src/mem/physical.cc14
6 files changed, 34 insertions, 35 deletions
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 086985f8d..fb8b7d81b 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -303,8 +303,8 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
void
AbstractMemory::access(PacketPtr pkt)
{
- assert(pkt->getAddr() >= range.start &&
- (pkt->getAddr() + pkt->getSize() - 1) <= range.end);
+ assert(AddrRange(pkt->getAddr(),
+ pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
if (pkt->memInhibitAsserted()) {
DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
@@ -312,7 +312,7 @@ AbstractMemory::access(PacketPtr pkt)
return;
}
- uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start;
+ uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
if (pkt->cmd == MemCmd::SwapReq) {
TheISA::IntReg overwrite_val;
@@ -384,10 +384,10 @@ AbstractMemory::access(PacketPtr pkt)
void
AbstractMemory::functionalAccess(PacketPtr pkt)
{
- assert(pkt->getAddr() >= range.start &&
- (pkt->getAddr() + pkt->getSize() - 1) <= range.end);
+ assert(AddrRange(pkt->getAddr(),
+ pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
- uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start;
+ uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
if (pkt->isRead()) {
if (pmemAddr)
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index d6d33c8ee..c1ecbdba4 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -266,7 +266,7 @@ class AbstractMemory : public MemObject
*
* @return the start address of the memory
*/
- Addr start() const { return range.start; }
+ Addr start() const { return range.start(); }
/**
* Should this memory be passed to the kernel and part of the OS
diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc
index b754cb7e6..660848c82 100644
--- a/src/mem/addr_mapper.cc
+++ b/src/mem/addr_mapper.cc
@@ -253,9 +253,9 @@ Addr
RangeAddrMapper::remapAddr(Addr addr) const
{
for (int i = 0; i < originalRanges.size(); ++i) {
- if (originalRanges[i] == addr) {
- Addr offset = addr - originalRanges[i].start;
- return offset + remappedRanges[i].start;
+ if (originalRanges[i].contains(addr)) {
+ Addr offset = addr - originalRanges[i].start();
+ return offset + remappedRanges[i].start();
}
}
@@ -277,11 +277,12 @@ RangeAddrMapper::getAddrRanges() const
" ranges but are not a subset.\n");
if (range.isSubset(originalRanges[j])) {
// range is a subset
- Addr offset = range.start - originalRanges[j].start;
- range.start -= offset;
- range.end -= offset;
+ Addr offset = range.start() - originalRanges[j].start();
+ Addr start = range.start() - offset;
+ ranges.push_back(AddrRange(start, start + range.size() - 1));
+ } else {
+ ranges.push_back(range);
}
- ranges.push_back(range);
}
}
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index ddbdcb136..e8a7084b0 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -357,7 +357,7 @@ BaseBus::findPort(Addr addr)
// Check if this matches the default range
if (useDefaultRange) {
- if (defaultRange == addr) {
+ if (defaultRange.contains(addr)) {
DPRINTF(BusAddrRanges, " found addr %#llx on default\n",
addr);
return defaultPortID;
@@ -430,8 +430,8 @@ BaseBus::recvRangeChange(PortID master_port_id)
AddrRangeList ranges = masterPorts[master_port_id]->getAddrRanges();
for (AddrRangeConstIter r = ranges.begin(); r != ranges.end(); ++r) {
- DPRINTF(BusAddrRanges, "Adding range %#llx : %#llx for id %d\n",
- r->start, r->end, master_port_id);
+ DPRINTF(BusAddrRanges, "Adding range %s for id %d\n",
+ r->to_string(), master_port_id);
if (portMap.insert(*r, master_port_id) == portMap.end()) {
PortID conflict_id = portMap.find(*r)->second;
fatal("%s has two ports with same range:\n\t%s\n\t%s\n",
@@ -466,9 +466,9 @@ BaseBus::recvRangeChange(PortID master_port_id)
// overlapping the default range
if (r->intersects(defaultRange) &&
!r->isSubset(defaultRange))
- fatal("Range %#llx : %#llx intersects the " \
+ fatal("Range %s intersects the " \
"default range of %s but is not a " \
- "subset\n", r->start, r->end, name());
+ "subset\n", r->to_string(), name());
}
}
}
@@ -497,18 +497,16 @@ BaseBus::getAddrRanges() const
// start out with the default range
AddrRangeList ranges;
ranges.push_back(defaultRange);
- DPRINTF(BusAddrRanges, " -- %#llx : %#llx DEFAULT\n",
- defaultRange.start, defaultRange.end);
+ DPRINTF(BusAddrRanges, " -- %s DEFAULT\n", defaultRange.to_string());
// add any range that is not a subset of the default range
for (PortMapConstIter p = portMap.begin(); p != portMap.end(); ++p) {
if (useDefaultRange && p->first.isSubset(defaultRange)) {
- DPRINTF(BusAddrRanges, " -- %#llx : %#llx is a SUBSET\n",
- p->first.start, p->first.end);
+ DPRINTF(BusAddrRanges, " -- %s is a SUBSET\n",
+ p->first.to_string());
} else {
ranges.push_back(p->first);
- DPRINTF(BusAddrRanges, " -- %#llx : %#llx\n",
- p->first.start, p->first.end);
+ DPRINTF(BusAddrRanges, " -- %s\n", p->first.to_string());
}
}
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 19ffa020c..59dabbfe4 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -264,13 +264,13 @@ class BaseBus : public MemObject
// Checks the cache and returns the id of the port that has the requested
// address within its range
inline PortID checkPortCache(Addr addr) const {
- if (portCache[0].valid && portCache[0].range == addr) {
+ if (portCache[0].valid && portCache[0].range.contains(addr)) {
return portCache[0].id;
}
- if (portCache[1].valid && portCache[1].range == addr) {
+ if (portCache[1].valid && portCache[1].range.contains(addr)) {
return portCache[1].id;
}
- if (portCache[2].valid && portCache[2].range == addr) {
+ if (portCache[2].valid && portCache[2].range.contains(addr)) {
return portCache[2].id;
}
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index b6f4c7a95..ef1f7159e 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -120,8 +120,8 @@ PhysicalMemory::createBackingStore(AddrRange range,
const vector<AbstractMemory*>& _memories)
{
// perform the actual mmap
- DPRINTF(BusAddrRanges, "Creating backing store for range %x:%x\n",
- range.start, range.end);
+ DPRINTF(BusAddrRanges, "Creating backing store for range %s\n",
+ range.to_string());
int map_flags = MAP_ANON | MAP_PRIVATE;
uint8_t* pmem = (uint8_t*) mmap(NULL, range.size(),
PROT_READ | PROT_WRITE,
@@ -129,8 +129,8 @@ PhysicalMemory::createBackingStore(AddrRange range,
if (pmem == (uint8_t*) MAP_FAILED) {
perror("mmap");
- fatal("Could not mmap %d bytes for range %x:%x!\n", range.size(),
- range.start, range.end);
+ fatal("Could not mmap %d bytes for range %s!\n", range.size(),
+ range.to_string());
}
// remember this backing store so we can checkpoint it and unmap
@@ -157,8 +157,8 @@ PhysicalMemory::createBackingStore(AddrRange range,
if (init_to_zero != 0) {
if (init_to_zero != _memories.size())
- fatal("Some, but not all memories in range %x:%x are set zero\n",
- range.start, range.end);
+ fatal("Some, but not all memories in range %s are set zero\n",
+ range.to_string());
memset(pmem, 0, range.size());
}
@@ -176,7 +176,7 @@ bool
PhysicalMemory::isMemAddr(Addr addr) const
{
// see if the address is within the last matched range
- if (addr != rangeCache) {
+ if (!rangeCache.contains(addr)) {
// lookup in the interval tree
AddrRangeMap<AbstractMemory*>::const_iterator r = addrMap.find(addr);
if (r == addrMap.end()) {