diff options
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/SerialLink.py | 2 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.hh | 3 | ||||
| -rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py | 34 | ||||
| -rw-r--r-- | src/mem/serial_link.cc | 15 | ||||
| -rw-r--r-- | src/mem/serial_link.hh | 3 |
5 files changed, 34 insertions, 23 deletions
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py index f05f2872d..fd9b0ff6b 100644 --- a/src/mem/SerialLink.py +++ b/src/mem/SerialLink.py @@ -61,3 +61,5 @@ class SerialLink(MemObject): # link belongs to and the number of lanes: num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial" "link. (aka. lane width)") + link_speed = Param.UInt64(1, "Gb/s Speed of each parallel lane inside the" + "serial link. (aka. lane speed)") diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index 6cd72b266..f59528492 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -41,6 +41,7 @@ * Ani Udipi * Neha Agarwal * Omar Naji + * Matthias Jung */ /** @@ -862,7 +863,7 @@ class DRAMCtrl : public AbstractMemory */ static bool sortTime(const Data::MemCommand& m1, const Data::MemCommand& m2) { - return m1.getTime() < m2.getTime(); + return m1.getTimeInt64() < m2.getTimeInt64(); }; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py index c7833ee96..5a4f3026e 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py @@ -53,19 +53,20 @@ class GarnetIntLink_d(BasicIntLink): cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh" # The detailed fixed pipeline bi-directional link include two main # forward links and two backward flow-control links, one per direction - nls = [] + _nls = [] # In uni-directional link - nls.append(NetworkLink_d()); + _nls.append(NetworkLink_d()); # Out uni-directional link - nls.append(NetworkLink_d()); - network_links = VectorParam.NetworkLink_d(nls, "forward links") + _nls.append(NetworkLink_d()); + network_links = VectorParam.NetworkLink_d(_nls, "forward links") - cls = [] + _cls = [] # In uni-directional link - cls.append(CreditLink_d()); + _cls.append(CreditLink_d()); # Out uni-directional link - cls.append(CreditLink_d()); - credit_links = VectorParam.CreditLink_d(cls, "backward flow-control links") + _cls.append(CreditLink_d()); + credit_links = VectorParam.CreditLink_d(_cls, + "backward flow-control links") # Exterior fixed pipeline links between a router and a controller class GarnetExtLink_d(BasicExtLink): @@ -73,16 +74,17 @@ class GarnetExtLink_d(BasicExtLink): cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh" # The detailed fixed pipeline bi-directional link include two main # forward links and two backward flow-control links, one per direction - nls = [] + _nls = [] # In uni-directional link - nls.append(NetworkLink_d()); + _nls.append(NetworkLink_d()); # Out uni-directional link - nls.append(NetworkLink_d()); - network_links = VectorParam.NetworkLink_d(nls, "forward links") + _nls.append(NetworkLink_d()); + network_links = VectorParam.NetworkLink_d(_nls, "forward links") - cls = [] + _cls = [] # In uni-directional link - cls.append(CreditLink_d()); + _cls.append(CreditLink_d()); # Out uni-directional link - cls.append(CreditLink_d()); - credit_links = VectorParam.CreditLink_d(cls, "backward flow-control links") + _cls.append(CreditLink_d()); + credit_links = VectorParam.CreditLink_d(_cls, + "backward flow-control links") diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc index b6cb097b7..25f5291bb 100644 --- a/src/mem/serial_link.cc +++ b/src/mem/serial_link.cc @@ -87,7 +87,9 @@ SerialLink::SerialLink(SerialLinkParams *p) ticksToCycles(p->delay), p->resp_size, p->ranges), masterPort(p->name + ".master", *this, slavePort, ticksToCycles(p->delay), p->req_size), - num_lanes(p->num_lanes) + num_lanes(p->num_lanes), + link_speed(p->link_speed) + { } @@ -153,8 +155,9 @@ SerialLink::SerialLinkMasterPort::recvTimingResp(PacketPtr pkt) // have to wait to receive the whole packet. So we only account for the // deserialization latency. Cycles cycles = delay; - cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes)); - Tick t = serial_link.clockEdge(cycles); + cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes + * serial_link.link_speed)); + Tick t = serial_link.clockEdge(cycles); //@todo: If the processor sends two uncached requests towards HMC and the // second one is smaller than the first one. It may happen that the second @@ -214,7 +217,7 @@ SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt) // only. Cycles cycles = delay; cycles += Cycles(divCeil(pkt->getSize() * 8, - serial_link.num_lanes)); + serial_link.num_lanes * serial_link.link_speed)); Tick t = serial_link.clockEdge(cycles); //@todo: If the processor sends two uncached requests towards HMC @@ -301,7 +304,7 @@ SerialLink::SerialLinkMasterPort::trySendTiming() // Make sure bandwidth limitation is met Cycles cycles = Cycles(divCeil(pkt->getSize() * 8, - serial_link.num_lanes)); + serial_link.num_lanes * serial_link.link_speed)); Tick t = serial_link.clockEdge(cycles); serial_link.schedule(sendEvent, std::max(next_req.tick, t)); } @@ -346,7 +349,7 @@ SerialLink::SerialLinkSlavePort::trySendTiming() // Make sure bandwidth limitation is met Cycles cycles = Cycles(divCeil(pkt->getSize() * 8, - serial_link.num_lanes)); + serial_link.num_lanes * serial_link.link_speed)); Tick t = serial_link.clockEdge(cycles); serial_link.schedule(sendEvent, std::max(next_resp.tick, t)); } diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh index d4f6ca488..9fbcce335 100644 --- a/src/mem/serial_link.hh +++ b/src/mem/serial_link.hh @@ -312,6 +312,9 @@ class SerialLink : public MemObject /** Number of parallel lanes in this serial link */ unsigned num_lanes; + /** Speed of each link (Gb/s) in this serial link */ + uint64_t link_speed; + public: virtual BaseMasterPort& getMasterPort(const std::string& if_name, |