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-rw-r--r--src/mem/bridge.cc7
-rw-r--r--src/mem/bridge.hh6
-rw-r--r--src/mem/cache/base.cc3
-rw-r--r--src/mem/cache/base.hh3
-rw-r--r--src/mem/cache/cache.cc3
-rw-r--r--src/mem/cache/cache.hh3
-rw-r--r--src/mem/comm_monitor.cc2
-rw-r--r--src/mem/comm_monitor.hh2
-rw-r--r--src/mem/dram_ctrl.cc11
-rw-r--r--src/mem/dram_ctrl.hh22
-rw-r--r--src/mem/dramsim2.cc3
-rw-r--r--src/mem/dramsim2.hh4
-rw-r--r--src/mem/serial_link.cc5
-rw-r--r--src/mem/serial_link.hh6
-rw-r--r--src/mem/simple_mem.cc3
-rw-r--r--src/mem/simple_mem.hh4
-rw-r--r--src/mem/xbar.cc2
-rw-r--r--src/mem/xbar.hh2
18 files changed, 45 insertions, 46 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index a7adcba64..0c9e2c15a 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -61,8 +61,8 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
std::vector<AddrRange> _ranges)
: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), ranges(_ranges.begin(), _ranges.end()),
- outstandingResponses(0), retryReq(false),
- respQueueLimit(_resp_limit), sendEvent(*this)
+ outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit),
+ sendEvent([this]{ trySendTiming(); }, _name)
{
}
@@ -71,7 +71,8 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
BridgeSlavePort& _slavePort,
Cycles _delay, int _req_limit)
: MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
- delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
+ delay(_delay), reqQueueLimit(_req_limit),
+ sendEvent([this]{ trySendTiming(); }, _name)
{
}
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index ad3585997..f2cc44501 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -156,8 +156,7 @@ class Bridge : public MemObject
void trySendTiming();
/** Send event for the response queue. */
- EventWrapper<BridgeSlavePort,
- &BridgeSlavePort::trySendTiming> sendEvent;
+ EventFunctionWrapper sendEvent;
public:
@@ -255,8 +254,7 @@ class Bridge : public MemObject
void trySendTiming();
/** Send event for the request queue. */
- EventWrapper<BridgeMasterPort,
- &BridgeMasterPort::trySendTiming> sendEvent;
+ EventFunctionWrapper sendEvent;
public:
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 7f08d173e..6f2532371 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -62,7 +62,8 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
: QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
- blocked(false), mustSendRetry(false), sendRetryEvent(this)
+ blocked(false), mustSendRetry(false),
+ sendRetryEvent([this]{ processSendRetry(); }, _name)
{
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 2787eea8c..2f4b934b3 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -177,8 +177,7 @@ class BaseCache : public MemObject
void processSendRetry();
- EventWrapper<CacheSlavePort,
- &CacheSlavePort::processSendRetry> sendRetryEvent;
+ EventFunctionWrapper sendRetryEvent;
};
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 09148100e..fdc14a7c0 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -73,7 +73,8 @@ Cache::Cache(const CacheParams *p)
clusivity(p->clusivity),
writebackClean(p->writeback_clean),
tempBlockWriteback(nullptr),
- writebackTempBlockAtomicEvent(this, false,
+ writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
+ name(), false,
EventBase::Delayed_Writeback_Pri)
{
tempBlock = new CacheBlk();
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index e5c8ab61f..9d135c652 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -257,8 +257,7 @@ class Cache : public BaseCache
* finishes. To avoid other calls to recvAtomic getting in
* between, we create this event with a higher priority.
*/
- EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
- writebackTempBlockAtomicEvent;
+ EventFunctionWrapper writebackTempBlockAtomicEvent;
/**
* Store the outstanding requests that we are expecting snoop
diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc
index 0914f34bb..354f66092 100644
--- a/src/mem/comm_monitor.cc
+++ b/src/mem/comm_monitor.cc
@@ -52,7 +52,7 @@ CommMonitor::CommMonitor(Params* params)
: MemObject(params),
masterPort(name() + "-master", *this),
slavePort(name() + "-slave", *this),
- samplePeriodicEvent(this),
+ samplePeriodicEvent([this]{ samplePeriodic(); }, name()),
samplePeriodTicks(params->sample_period),
samplePeriod(params->sample_period / SimClock::Float::s),
stats(params)
diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh
index fa28eaee4..d27594d23 100644
--- a/src/mem/comm_monitor.hh
+++ b/src/mem/comm_monitor.hh
@@ -410,7 +410,7 @@ class CommMonitor : public MemObject
void samplePeriodic();
/** Periodic event called at the end of each simulation time bin */
- EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent;
+ EventFunctionWrapper samplePeriodicEvent;
/**
*@{
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 9e5c00b0e..da494a1d2 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -63,7 +63,8 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
retryRdReq(false), retryWrReq(false),
busState(READ),
busStateNext(READ),
- nextReqEvent(this), respondEvent(this),
+ nextReqEvent([this]{ processNextReqEvent(); }, name()),
+ respondEvent([this]{ processRespondEvent(); }, name()),
deviceSize(p->device_size),
deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
deviceRowBufferSize(p->device_rowbuffer_size),
@@ -1610,8 +1611,12 @@ DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank)
readEntries(0), writeEntries(0), outstandingEvents(0),
wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank),
numBanksActive(0), actTicks(_p->activation_limit, 0),
- writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
- refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
+ writeDoneEvent([this]{ processWriteDoneEvent(); }, name()),
+ activateEvent([this]{ processActivateEvent(); }, name()),
+ prechargeEvent([this]{ processPrechargeEvent(); }, name()),
+ refreshEvent([this]{ processRefreshEvent(); }, name()),
+ powerEvent([this]{ processPowerEvent(); }, name()),
+ wakeUpEvent([this]{ processWakeUpEvent(); }, name())
{
for (int b = 0; b < _p->banks_per_rank; b++) {
banks[b].bank = b;
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 1883041cc..226897b7e 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -556,28 +556,22 @@ class DRAMCtrl : public AbstractMemory
void scheduleWakeUpEvent(Tick exit_delay);
void processWriteDoneEvent();
- EventWrapper<Rank, &Rank::processWriteDoneEvent>
- writeDoneEvent;
+ EventFunctionWrapper writeDoneEvent;
void processActivateEvent();
- EventWrapper<Rank, &Rank::processActivateEvent>
- activateEvent;
+ EventFunctionWrapper activateEvent;
void processPrechargeEvent();
- EventWrapper<Rank, &Rank::processPrechargeEvent>
- prechargeEvent;
+ EventFunctionWrapper prechargeEvent;
void processRefreshEvent();
- EventWrapper<Rank, &Rank::processRefreshEvent>
- refreshEvent;
+ EventFunctionWrapper refreshEvent;
void processPowerEvent();
- EventWrapper<Rank, &Rank::processPowerEvent>
- powerEvent;
+ EventFunctionWrapper powerEvent;
void processWakeUpEvent();
- EventWrapper<Rank, &Rank::processWakeUpEvent>
- wakeUpEvent;
+ EventFunctionWrapper wakeUpEvent;
};
@@ -685,10 +679,10 @@ class DRAMCtrl : public AbstractMemory
* in these methods
*/
void processNextReqEvent();
- EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
+ EventFunctionWrapper nextReqEvent;
void processRespondEvent();
- EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
+ EventFunctionWrapper respondEvent;
/**
* Check if the read queue has room for more entries
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index 106ea264f..b900d4df0 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -53,7 +53,8 @@ DRAMSim2::DRAMSim2(const Params* p) :
p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
- sendResponseEvent(this), tickEvent(this)
+ sendResponseEvent([this]{ sendResponse(); }, name()),
+ tickEvent([this]{ tick(); }, name())
{
DPRINTF(DRAMSim2,
"Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 5cde19cd8..6444f75d6 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -148,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
/**
* Event to schedule sending of responses
*/
- EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+ EventFunctionWrapper sendResponseEvent;
/**
* Progress the controller one clock cycle.
@@ -158,7 +158,7 @@ class DRAMSim2 : public AbstractMemory
/**
* Event to schedule clock ticks
*/
- EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+ EventFunctionWrapper tickEvent;
/**
* Upstream caches need this packet until true is returned, so
diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc
index ee21163b7..97563c0d0 100644
--- a/src/mem/serial_link.cc
+++ b/src/mem/serial_link.cc
@@ -66,7 +66,8 @@ SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string& _name,
masterPort(_masterPort), delay(_delay),
ranges(_ranges.begin(), _ranges.end()),
outstandingResponses(0), retryReq(false),
- respQueueLimit(_resp_limit), sendEvent(*this)
+ respQueueLimit(_resp_limit),
+ sendEvent([this]{ trySendTiming(); }, _name)
{
}
@@ -76,7 +77,7 @@ SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
Cycles _delay, int _req_limit)
: MasterPort(_name, &_serial_link), serial_link(_serial_link),
slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
- sendEvent(*this)
+ sendEvent([this]{ trySendTiming(); }, _name)
{
}
diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh
index 9fbcce335..64f262d0f 100644
--- a/src/mem/serial_link.hh
+++ b/src/mem/serial_link.hh
@@ -146,8 +146,7 @@ class SerialLink : public MemObject
void trySendTiming();
/** Send event for the response queue. */
- EventWrapper<SerialLinkSlavePort,
- &SerialLinkSlavePort::trySendTiming> sendEvent;
+ EventFunctionWrapper sendEvent;
public:
@@ -247,8 +246,7 @@ class SerialLink : public MemObject
void trySendTiming();
/** Send event for the request queue. */
- EventWrapper<SerialLinkMasterPort,
- &SerialLinkMasterPort::trySendTiming> sendEvent;
+ EventFunctionWrapper sendEvent;
public:
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index f524d01ab..8358a828b 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -55,7 +55,8 @@ SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
port(name() + ".port", *this), latency(p->latency),
latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
retryReq(false), retryResp(false),
- releaseEvent(this), dequeueEvent(this)
+ releaseEvent([this]{ release(); }, name()),
+ dequeueEvent([this]{ dequeue(); }, name())
{
}
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 23cd3c80d..6636f2c90 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -158,7 +158,7 @@ class SimpleMemory : public AbstractMemory
*/
void release();
- EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
+ EventFunctionWrapper releaseEvent;
/**
* Dequeue a packet from our internal packet queue and move it to
@@ -166,7 +166,7 @@ class SimpleMemory : public AbstractMemory
*/
void dequeue();
- EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent;
+ EventFunctionWrapper dequeueEvent;
/**
* Detemine the latency.
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 035461944..b7826fd25 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -147,7 +147,7 @@ template <typename SrcType, typename DstType>
BaseXBar::Layer<SrcType,DstType>::Layer(DstType& _port, BaseXBar& _xbar,
const std::string& _name) :
port(_port), xbar(_xbar), _name(_name), state(IDLE),
- waitingForPeer(NULL), releaseEvent(this)
+ waitingForPeer(NULL), releaseEvent([this]{ releaseLayer(); }, name())
{
}
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index c9949e364..f826e142a 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -237,7 +237,7 @@ class BaseXBar : public MemObject
void releaseLayer();
/** event used to schedule a release of the layer */
- EventWrapper<Layer, &Layer::releaseLayer> releaseEvent;
+ EventFunctionWrapper releaseEvent;
/**
* Stats for occupancy and utilization. These stats capture
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:06:20 +0000