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-rw-r--r--src/mem/abstract_mem.cc7
-rw-r--r--src/mem/abstract_mem.hh4
-rw-r--r--src/mem/bridge.cc2
-rw-r--r--src/mem/bridge.hh2
-rw-r--r--src/mem/bus.cc3
-rw-r--r--src/mem/bus.hh9
-rw-r--r--src/mem/cache/cache_impl.hh1
-rw-r--r--src/mem/physical.cc8
-rw-r--r--src/mem/physical.hh6
-rw-r--r--src/mem/port.hh8
10 files changed, 22 insertions, 28 deletions
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 775517e3b..ebe4a64b5 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -85,9 +85,8 @@ AbstractMemory::AbstractMemory(const Params *p) :
int fd = open(params()->file.c_str(), O_RDONLY);
long _size = lseek(fd, 0, SEEK_END);
if (_size != range.size()) {
- warn("Specified size %d does not match file %s %d\n", range.size(),
- params()->file, _size);
- range = RangeSize(range.start, _size);
+ fatal("Specified size %d does not match file %s %d\n",
+ range.size(), params()->file, _size);
}
lseek(fd, 0, SEEK_SET);
pmemAddr = (uint8_t *)mmap(NULL, roundUp(_size, sysconf(_SC_PAGESIZE)),
@@ -222,7 +221,7 @@ AbstractMemory::regStats()
bwTotal = (bytesRead + bytesWritten) / simSeconds;
}
-Range<Addr>
+AddrRange
AbstractMemory::getAddrRange() const
{
return range;
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 43d9656da..66d4a1f16 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -68,7 +68,7 @@ class AbstractMemory : public MemObject
protected:
// Address range of this memory
- Range<Addr> range;
+ AddrRange range;
// Pointer to host memory used to implement this memory
uint8_t* pmemAddr;
@@ -209,7 +209,7 @@ class AbstractMemory : public MemObject
*
* @return a single contigous address range
*/
- Range<Addr> getAddrRange() const;
+ AddrRange getAddrRange() const;
/**
* Get the memory size.
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 3a185a8eb..8bc34e12e 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -57,7 +57,7 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
Bridge& _bridge,
BridgeMasterPort& _masterPort,
Cycles _delay, int _resp_limit,
- std::vector<Range<Addr> > _ranges)
+ std::vector<AddrRange> _ranges)
: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), ranges(_ranges.begin(), _ranges.end()),
outstandingResponses(0), retryReq(false),
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index c52146463..eb0b2434f 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -193,7 +193,7 @@ class Bridge : public MemObject
*/
BridgeSlavePort(const std::string& _name, Bridge& _bridge,
BridgeMasterPort& _masterPort, Cycles _delay,
- int _resp_limit, std::vector<Range<Addr> > _ranges);
+ int _resp_limit, std::vector<AddrRange> _ranges);
/**
* Queue a response packet to be sent out later and also schedule
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 829d694de..75ece9bc8 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -355,7 +355,6 @@ BaseBus::findPort(Addr addr)
void
BaseBus::recvRangeChange(PortID master_port_id)
{
- AddrRangeList ranges;
AddrRangeIter iter;
if (inRecvRangeChange.count(master_port_id))
@@ -394,7 +393,7 @@ BaseBus::recvRangeChange(PortID master_port_id)
}
// get the address ranges of the connected slave port
- ranges = port->getAddrRanges();
+ AddrRangeList ranges = port->getAddrRanges();
for (iter = ranges.begin(); iter != ranges.end(); iter++) {
DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for id %d\n",
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index ac35581b1..541e2f363 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -54,8 +54,7 @@
#include <list>
#include <set>
-#include "base/range.hh"
-#include "base/range_map.hh"
+#include "base/addr_range_map.hh"
#include "base/types.hh"
#include "mem/mem_object.hh"
#include "params/BaseBus.hh"
@@ -233,9 +232,9 @@ class BaseBus : public MemObject
/** the width of the bus in bytes */
int width;
- typedef range_map<Addr, PortID>::iterator PortMapIter;
- typedef range_map<Addr, PortID>::const_iterator PortMapConstIter;
- range_map<Addr, PortID> portMap;
+ typedef AddrRangeMap<PortID>::iterator PortMapIter;
+ typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter;
+ AddrRangeMap<PortID> portMap;
AddrRangeList defaultRange;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 563160ac1..9b9010d34 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -51,7 +51,6 @@
*/
#include "base/misc.hh"
-#include "base/range.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 5f92976f9..23556f0ab 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -64,7 +64,6 @@ PhysicalMemory::PhysicalMemory(const vector<AbstractMemory*>& _memories) :
"Skipping memory %s that is not in global address map\n",
(*m)->name());
}
- rangeCache.invalidate();
}
bool
@@ -73,8 +72,7 @@ PhysicalMemory::isMemAddr(Addr addr) const
// see if the address is within the last matched range
if (addr != rangeCache) {
// lookup in the interval tree
- range_map<Addr, AbstractMemory*>::const_iterator r =
- addrMap.find(addr);
+ AddrRangeMap<AbstractMemory*>::const_iterator r = addrMap.find(addr);
if (r == addrMap.end()) {
// not in the cache, and not in the tree
return false;
@@ -110,7 +108,7 @@ PhysicalMemory::access(PacketPtr pkt)
{
assert(pkt->isRequest());
Addr addr = pkt->getAddr();
- range_map<Addr, AbstractMemory*>::const_iterator m = addrMap.find(addr);
+ AddrRangeMap<AbstractMemory*>::const_iterator m = addrMap.find(addr);
assert(m != addrMap.end());
m->second->access(pkt);
}
@@ -120,7 +118,7 @@ PhysicalMemory::functionalAccess(PacketPtr pkt)
{
assert(pkt->isRequest());
Addr addr = pkt->getAddr();
- range_map<Addr, AbstractMemory*>::const_iterator m = addrMap.find(addr);
+ AddrRangeMap<AbstractMemory*>::const_iterator m = addrMap.find(addr);
assert(m != addrMap.end());
m->second->functionalAccess(pkt);
}
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index e78b1d2da..fb9969a34 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -40,7 +40,7 @@
#ifndef __PHYSICAL_MEMORY_HH__
#define __PHYSICAL_MEMORY_HH__
-#include "base/range_map.hh"
+#include "base/addr_range_map.hh"
#include "mem/abstract_mem.hh"
#include "mem/packet.hh"
@@ -55,10 +55,10 @@ class PhysicalMemory
private:
// Global address map
- range_map<Addr, AbstractMemory* > addrMap;
+ AddrRangeMap<AbstractMemory*> addrMap;
// a mutable cache for the last range that matched an address
- mutable Range<Addr> rangeCache;
+ mutable AddrRange rangeCache;
// All address-mapped memories
std::vector<AbstractMemory*> memories;
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 631725ce1..eaad9668a 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -52,7 +52,7 @@
#include <list>
-#include "base/range.hh"
+#include "base/addr_range.hh"
#include "mem/packet.hh"
/**
@@ -62,9 +62,9 @@
* defined.
*/
-typedef std::list<Range<Addr> > AddrRangeList;
-typedef std::list<Range<Addr> >::iterator AddrRangeIter;
-typedef std::list<Range<Addr> >::const_iterator AddrRangeConstIter;
+typedef std::list<AddrRange> AddrRangeList;
+typedef std::list<AddrRange>::iterator AddrRangeIter;
+typedef std::list<AddrRange>::const_iterator AddrRangeConstIter;
class MemObject;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 23:03:17 +0000